Re: [PATCH] clk: tegra: Fix PLLE programming

2014-04-02 Thread Peter De Schrijver
On Mon, Mar 31, 2014 at 09:46:22PM +0200, Thierry Reding wrote: > * PGP Signed by an unknown key > > On Mon, Mar 31, 2014 at 10:51:38AM -0600, Stephen Warren wrote: > > On 03/31/2014 08:45 AM, Thierry Reding wrote: > > > From: Thierry Reding > > > > > > PLLE has M, N and P divider shift and

Re: [PATCH] clk: tegra: Fix PLLE programming

2014-04-02 Thread Peter De Schrijver
On Mon, Mar 31, 2014 at 09:46:22PM +0200, Thierry Reding wrote: * PGP Signed by an unknown key On Mon, Mar 31, 2014 at 10:51:38AM -0600, Stephen Warren wrote: On 03/31/2014 08:45 AM, Thierry Reding wrote: From: Thierry Reding tred...@nvidia.com PLLE has M, N and P divider shift and

Re: [PATCH] clk: tegra: Fix PLLE programming

2014-03-31 Thread Thierry Reding
On Mon, Mar 31, 2014 at 10:51:38AM -0600, Stephen Warren wrote: > On 03/31/2014 08:45 AM, Thierry Reding wrote: > > From: Thierry Reding > > > > PLLE has M, N and P divider shift and width parameters that differ from > > the defaults. Furthermore, when clearing the M, N and P divider fields > >

Re: [PATCH] clk: tegra: Fix PLLE programming

2014-03-31 Thread Stephen Warren
On 03/31/2014 08:45 AM, Thierry Reding wrote: > From: Thierry Reding > > PLLE has M, N and P divider shift and width parameters that differ from > the defaults. Furthermore, when clearing the M, N and P divider fields > the corresponding masks were never shifted, thereby clearing only the >

[PATCH] clk: tegra: Fix PLLE programming

2014-03-31 Thread Thierry Reding
From: Thierry Reding PLLE has M, N and P divider shift and width parameters that differ from the defaults. Furthermore, when clearing the M, N and P divider fields the corresponding masks were never shifted, thereby clearing only the lowest bits of the register. This lead to a situation where

[PATCH] clk: tegra: Fix PLLE programming

2014-03-31 Thread Thierry Reding
From: Thierry Reding tred...@nvidia.com PLLE has M, N and P divider shift and width parameters that differ from the defaults. Furthermore, when clearing the M, N and P divider fields the corresponding masks were never shifted, thereby clearing only the lowest bits of the register. This lead to a

Re: [PATCH] clk: tegra: Fix PLLE programming

2014-03-31 Thread Stephen Warren
On 03/31/2014 08:45 AM, Thierry Reding wrote: From: Thierry Reding tred...@nvidia.com PLLE has M, N and P divider shift and width parameters that differ from the defaults. Furthermore, when clearing the M, N and P divider fields the corresponding masks were never shifted, thereby clearing

Re: [PATCH] clk: tegra: Fix PLLE programming

2014-03-31 Thread Thierry Reding
On Mon, Mar 31, 2014 at 10:51:38AM -0600, Stephen Warren wrote: On 03/31/2014 08:45 AM, Thierry Reding wrote: From: Thierry Reding tred...@nvidia.com PLLE has M, N and P divider shift and width parameters that differ from the defaults. Furthermore, when clearing the M, N and P divider