On Mon, Mar 31, 2014 at 09:46:22PM +0200, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Mon, Mar 31, 2014 at 10:51:38AM -0600, Stephen Warren wrote:
> > On 03/31/2014 08:45 AM, Thierry Reding wrote:
> > > From: Thierry Reding
> > >
> > > PLLE has M, N and P divider shift and
On Mon, Mar 31, 2014 at 09:46:22PM +0200, Thierry Reding wrote:
* PGP Signed by an unknown key
On Mon, Mar 31, 2014 at 10:51:38AM -0600, Stephen Warren wrote:
On 03/31/2014 08:45 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
PLLE has M, N and P divider shift and
On Mon, Mar 31, 2014 at 10:51:38AM -0600, Stephen Warren wrote:
> On 03/31/2014 08:45 AM, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > PLLE has M, N and P divider shift and width parameters that differ from
> > the defaults. Furthermore, when clearing the M, N and P divider fields
> >
On 03/31/2014 08:45 AM, Thierry Reding wrote:
> From: Thierry Reding
>
> PLLE has M, N and P divider shift and width parameters that differ from
> the defaults. Furthermore, when clearing the M, N and P divider fields
> the corresponding masks were never shifted, thereby clearing only the
>
From: Thierry Reding
PLLE has M, N and P divider shift and width parameters that differ from
the defaults. Furthermore, when clearing the M, N and P divider fields
the corresponding masks were never shifted, thereby clearing only the
lowest bits of the register. This lead to a situation where
From: Thierry Reding tred...@nvidia.com
PLLE has M, N and P divider shift and width parameters that differ from
the defaults. Furthermore, when clearing the M, N and P divider fields
the corresponding masks were never shifted, thereby clearing only the
lowest bits of the register. This lead to a
On 03/31/2014 08:45 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
PLLE has M, N and P divider shift and width parameters that differ from
the defaults. Furthermore, when clearing the M, N and P divider fields
the corresponding masks were never shifted, thereby clearing
On Mon, Mar 31, 2014 at 10:51:38AM -0600, Stephen Warren wrote:
On 03/31/2014 08:45 AM, Thierry Reding wrote:
From: Thierry Reding tred...@nvidia.com
PLLE has M, N and P divider shift and width parameters that differ from
the defaults. Furthermore, when clearing the M, N and P divider
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