Re: [PATCH] drivers/perf: arm-pmu: Handle per-interrupt affinity mask

2016-07-06 Thread Marc Zyngier
On 06/07/16 11:39, Will Deacon wrote: > On Fri, Jul 01, 2016 at 02:21:31PM +0100, Marc Zyngier wrote: >> On a big-little system, PMUs can be wired to CPUs using per CPU >> interrups (PPI). In this case, it is important to make sure that >> the enable/disable do happen on the right set of CPUs. >>

Re: [PATCH] drivers/perf: arm-pmu: Handle per-interrupt affinity mask

2016-07-06 Thread Marc Zyngier
On 06/07/16 11:39, Will Deacon wrote: > On Fri, Jul 01, 2016 at 02:21:31PM +0100, Marc Zyngier wrote: >> On a big-little system, PMUs can be wired to CPUs using per CPU >> interrups (PPI). In this case, it is important to make sure that >> the enable/disable do happen on the right set of CPUs. >>

Re: [PATCH] drivers/perf: arm-pmu: Handle per-interrupt affinity mask

2016-07-06 Thread Will Deacon
On Fri, Jul 01, 2016 at 02:21:31PM +0100, Marc Zyngier wrote: > On a big-little system, PMUs can be wired to CPUs using per CPU > interrups (PPI). In this case, it is important to make sure that > the enable/disable do happen on the right set of CPUs. > > So instead of relying on the

Re: [PATCH] drivers/perf: arm-pmu: Handle per-interrupt affinity mask

2016-07-06 Thread Will Deacon
On Fri, Jul 01, 2016 at 02:21:31PM +0100, Marc Zyngier wrote: > On a big-little system, PMUs can be wired to CPUs using per CPU > interrups (PPI). In this case, it is important to make sure that > the enable/disable do happen on the right set of CPUs. > > So instead of relying on the

Re: [PATCH] drivers/perf: arm-pmu: Handle per-interrupt affinity mask

2016-07-05 Thread Rob Herring
On Fri, Jul 01, 2016 at 02:21:31PM +0100, Marc Zyngier wrote: > On a big-little system, PMUs can be wired to CPUs using per CPU > interrups (PPI). In this case, it is important to make sure that > the enable/disable do happen on the right set of CPUs. > > So instead of relying on the

Re: [PATCH] drivers/perf: arm-pmu: Handle per-interrupt affinity mask

2016-07-05 Thread Rob Herring
On Fri, Jul 01, 2016 at 02:21:31PM +0100, Marc Zyngier wrote: > On a big-little system, PMUs can be wired to CPUs using per CPU > interrups (PPI). In this case, it is important to make sure that > the enable/disable do happen on the right set of CPUs. > > So instead of relying on the

Re: [PATCH] drivers/perf: arm-pmu: Handle per-interrupt affinity mask

2016-07-01 Thread Caesar Wang
Hi Marc, On 2016年07月01日 21:21, Marc Zyngier wrote: On a big-little system, PMUs can be wired to CPUs using per CPU interrups (PPI). In this case, it is important to make sure that the enable/disable do happen on the right set of CPUs. So instead of relying on the interrupt-affinity property,

Re: [PATCH] drivers/perf: arm-pmu: Handle per-interrupt affinity mask

2016-07-01 Thread Caesar Wang
Hi Marc, On 2016年07月01日 21:21, Marc Zyngier wrote: On a big-little system, PMUs can be wired to CPUs using per CPU interrups (PPI). In this case, it is important to make sure that the enable/disable do happen on the right set of CPUs. So instead of relying on the interrupt-affinity property,

[PATCH] drivers/perf: arm-pmu: Handle per-interrupt affinity mask

2016-07-01 Thread Marc Zyngier
On a big-little system, PMUs can be wired to CPUs using per CPU interrups (PPI). In this case, it is important to make sure that the enable/disable do happen on the right set of CPUs. So instead of relying on the interrupt-affinity property, we can use the actual percpu affinity that DT exposes

[PATCH] drivers/perf: arm-pmu: Handle per-interrupt affinity mask

2016-07-01 Thread Marc Zyngier
On a big-little system, PMUs can be wired to CPUs using per CPU interrups (PPI). In this case, it is important to make sure that the enable/disable do happen on the right set of CPUs. So instead of relying on the interrupt-affinity property, we can use the actual percpu affinity that DT exposes