On Sat, 30 Jan 2021 at 05:00, Benjamin Li wrote:
>
>
> On 10/30/20 6:55 AM, Dmitry Baryshkov wrote:
> > Hello,
> >
> > On 07/10/2020 03:10, benl-kernelpatc...@squareup.com wrote:
> >> From: Benjamin Li
> >>
> >> Take advantage of previously-added support for persisting PLL
> >> registers across
On 10/30/20 6:55 AM, Dmitry Baryshkov wrote:
> Hello,
>
> On 07/10/2020 03:10, benl-kernelpatc...@squareup.com wrote:
>> From: Benjamin Li
>>
>> Take advantage of previously-added support for persisting PLL
>> registers across DSI PHY disable/enable cycles (see 328e1a6
>> 'drm/msm/dsi:
Hello,
On 07/10/2020 03:10, benl-kernelpatc...@squareup.com wrote:
From: Benjamin Li
Take advantage of previously-added support for persisting PLL
registers across DSI PHY disable/enable cycles (see 328e1a6
'drm/msm/dsi: Save/Restore PLL status across PHY reset') to
support persisting across
From: Benjamin Li
Take advantage of previously-added support for persisting PLL
registers across DSI PHY disable/enable cycles (see 328e1a6
'drm/msm/dsi: Save/Restore PLL status across PHY reset') to
support persisting across the very first DSI PHY enable at
boot.
The bootloader may have left
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