On Thu, Dec 11, 2014 at 02:26:41PM +0800, Jisheng Zhang wrote:
> readl/writel is too expensive especially on Cortex A9 w/ outer L2 cache.
> This introduces i2c read/write errors on Marvell BG2/BG2Q SoCs when there
> are heavy L2 cache maintenance operations at the same time.
>
> The driver does no
Dear Wolfram,
On Tue, 13 Jan 2015 06:36:54 -0800
Wolfram Sang wrote:
>
> On Thu, Dec 11, 2014 at 02:26:41PM +0800, Jisheng Zhang wrote:
> > readl/writel is too expensive especially on Cortex A9 w/ outer L2 cache.
> > This introduces i2c read/write errors on Marvell BG2/BG2Q SoCs when there
> >
Hi Wolfram,
On Tue, Jan 13, 2015 at 03:36:54PM +0100, Wolfram Sang wrote:
> > The driver does not perform DMA, so it's safe to use the relaxed version.
> > From another side, the relaxed io accessor macros are available on all
> > architectures now, so we can use the relaxed versions instead.
>
>
On Thu, Dec 11, 2014 at 02:26:41PM +0800, Jisheng Zhang wrote:
> readl/writel is too expensive especially on Cortex A9 w/ outer L2 cache.
> This introduces i2c read/write errors on Marvell BG2/BG2Q SoCs when there
> are heavy L2 cache maintenance operations at the same time.
Reading this again, I
On Tue, Jan 13, 2015 at 12:52:05PM +0100, Wolfram Sang wrote:
> On Fri, Dec 19, 2014 at 10:43:15AM +0800, Jisheng Zhang wrote:
> > Dear all,
> >
> > Is there any issue I need to resolve so that the patch can be merged?
>
> Adding Mika to the loop. He uses the driver a lot (and knows other
> peopl
On Fri, Dec 19, 2014 at 10:43:15AM +0800, Jisheng Zhang wrote:
> Dear all,
>
> Is there any issue I need to resolve so that the patch can be merged?
Adding Mika to the loop. He uses the driver a lot (and knows other
people who do)...
> On Wed, 10 Dec 2014 22:26:41 -0800
> Jisheng Zhang wrote:
Dear all,
Is there any issue I need to resolve so that the patch can be merged?
Thanks in advance,
Jisheng
On Wed, 10 Dec 2014 22:26:41 -0800
Jisheng Zhang wrote:
> readl/writel is too expensive especially on Cortex A9 w/ outer L2 cache.
> This introduces i2c read/write errors on Marvell BG2/B
readl/writel is too expensive especially on Cortex A9 w/ outer L2 cache.
This introduces i2c read/write errors on Marvell BG2/BG2Q SoCs when there
are heavy L2 cache maintenance operations at the same time.
The driver does not perform DMA, so it's safe to use the relaxed version.
>From another sid
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