On Friday 17 November 2006 23:57, Jeremy Fitzhardinge wrote:
> Andi Kleen wrote:
> > I have had private patches for that myself, using the MSRs on AMD
> > and Intel.
> >
>
> Would they be something that could be cleaned up into something
> mergeable?
Hmm maybe.
> It would be nice to have so
Andi Kleen wrote:
> I have had private patches for that myself, using the MSRs on AMD
> and Intel.
>
Would they be something that could be cleaned up into something
mergeable? It would be nice to have something that could be left
enabled all the time, but an option would at least make the
func
On Fri, Nov 17, 2006 at 10:22:20AM +0100, Andi Kleen wrote:
> > The former
> > stores from/to information into MSRs and is very small (4 branches).
>
> P4 since Prescott has 16
>
Yes. I was talking about Core 2
> > On recent processors LBR and BTS can be constrained by priv level.
>
> Doesn't
> The former
> stores from/to information into MSRs and is very small (4 branches).
P4 since Prescott has 16
> On recent processors LBR and BTS can be constrained by priv level.
Doesn't help for kernel debugging.
-Andi
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Jeremy,
On Fri, Nov 17, 2006 at 05:29:02AM +0100, Andi Kleen wrote:
> On Friday 17 November 2006 02:34, Jeremy Fitzhardinge wrote:
> > Stephane Eranian wrote:
> > > Here is a small patch that adds two cpufeature bits to represent
> > > Intel's Precise-Event-Based Sampling (PEBS) and Branch Trace S
On Friday 17 November 2006 02:34, Jeremy Fitzhardinge wrote:
> Stephane Eranian wrote:
> > Here is a small patch that adds two cpufeature bits to represent
> > Intel's Precise-Event-Based Sampling (PEBS) and Branch Trace Store
> > (BTS) features. Those features can be found on Intel P4 and Core 2
Stephane Eranian wrote:
> Here is a small patch that adds two cpufeature bits to represent
> Intel's Precise-Event-Based Sampling (PEBS) and Branch Trace Store
> (BTS) features. Those features can be found on Intel P4 and Core 2
> processors among others and can be used by perfmon.
>
I've been
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