Re: [PATCH] iio: adc: ti-ads7950: inconsistency with spi msg

Hello Florian On Thu, Jan 24, 2019 at 8:30 PM Florian Fainelli wrote: > > > Hi Justin, > > On 1/24/19 5:56 PM, justinpo...@gmail.com wrote: > > From: Justin Chen > > > > To read a channel we require 3 cycles to send, process, and receive > > the data. The transfer buffer for the third

Re: [PATCH] iio: adc: ti-ads7950: inconsistency with spi msg

Hi Justin, On 1/24/19 5:56 PM, justinpo...@gmail.com wrote: > From: Justin Chen > > To read a channel we require 3 cycles to send, process, and receive > the data. The transfer buffer for the third transaction is left blank. > This leaves it up to the SPI driver to decide what to do. > > In

[PATCH] iio: adc: ti-ads7950: inconsistency with spi msg

From: Justin Chen To read a channel we require 3 cycles to send, process, and receive the data. The transfer buffer for the third transaction is left blank. This leaves it up to the SPI driver to decide what to do. In one particular case, if the tx buffer is not set the spi driver sets it to