On 07.04.2017 10:32, Marc Zyngier wrote:
On 07/04/17 07:49, Mikko Perttunen wrote:
On 06.04.2017 12:26, Marc Zyngier wrote:
On 06/04/17 09:17, Mikko Perttunen wrote:
From: Matt Craighead
According to the GICv2 specification, the GICD_ICFGR0,
or GIC_DIST_CONFIG[0] register is read-only. There
On 07/04/17 07:49, Mikko Perttunen wrote:
> On 06.04.2017 12:26, Marc Zyngier wrote:
>> On 06/04/17 09:17, Mikko Perttunen wrote:
>>> From: Matt Craighead
>>>
>>> According to the GICv2 specification, the GICD_ICFGR0,
>>> or GIC_DIST_CONFIG[0] register is read-only. Therefore
>>> avoid writing to
On 06.04.2017 12:26, Marc Zyngier wrote:
On 06/04/17 09:17, Mikko Perttunen wrote:
From: Matt Craighead
According to the GICv2 specification, the GICD_ICFGR0,
or GIC_DIST_CONFIG[0] register is read-only. Therefore
avoid writing to it.
Have you verified that this also applies to pre-v2 GICs?
On 06/04/17 09:17, Mikko Perttunen wrote:
> From: Matt Craighead
>
> According to the GICv2 specification, the GICD_ICFGR0,
> or GIC_DIST_CONFIG[0] register is read-only. Therefore
> avoid writing to it.
Have you verified that this also applies to pre-v2 GICs?
>
> Signed-off-by: Matt Craighead
From: Matt Craighead
According to the GICv2 specification, the GICD_ICFGR0,
or GIC_DIST_CONFIG[0] register is read-only. Therefore
avoid writing to it.
Signed-off-by: Matt Craighead
[mperttu...@nvidia.com: commit message rewritten]
Signed-off-by: Mikko Perttunen
---
drivers/irqchip/irq-gic.c
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