Hi Christophe, Boris,
On Tue, May 02, 2017 at 11:03:34AM +0200, Boris Brezillon wrote:
> On Tue, 2 May 2017 07:47:40 +0200
> Christophe LEROY wrote:
>
> > Le 01/05/2017 à 23:46, Brian Norris a écrit :
> > > On Fri, Feb 10, 2017 at 03:01:10PM +0100, Christophe Leroy wrote:
> > >> On some hardwa
On Tue, 2 May 2017 07:47:40 +0200
Christophe LEROY wrote:
> Le 01/05/2017 à 23:46, Brian Norris a écrit :
> > On Fri, Feb 10, 2017 at 03:01:10PM +0100, Christophe Leroy wrote:
> >> On some hardware, the nCE signal is wired to the ChipSelect associated
> >> to bus address of the NAND, so it is a
Le 01/05/2017 à 23:46, Brian Norris a écrit :
On Fri, Feb 10, 2017 at 03:01:10PM +0100, Christophe Leroy wrote:
On some hardware, the nCE signal is wired to the ChipSelect associated
to bus address of the NAND, so it is automatically driven during the
memory access and it is not managed by a G
On Fri, Feb 10, 2017 at 03:01:10PM +0100, Christophe Leroy wrote:
> On some hardware, the nCE signal is wired to the ChipSelect associated
> to bus address of the NAND, so it is automatically driven during the
> memory access and it is not managed by a GPIO.
>
> Signed-off-by: Christophe Leroy
N
On Fri, 10 Feb 2017 15:01:10 +0100 (CET)
Christophe Leroy wrote:
> On some hardware, the nCE signal is wired to the ChipSelect associated
> to bus address of the NAND, so it is automatically driven during the
> memory access and it is not managed by a GPIO.
Applied.
Thanks,
Boris
>
> Signed-
On Mon, 13 Feb 2017 13:58:24 +0100
Christophe LEROY wrote:
> Le 13/02/2017 à 11:30, Boris Brezillon a écrit :
> > On Fri, 10 Feb 2017 15:01:10 +0100 (CET)
> > Christophe Leroy wrote:
> >
> >> On some hardware, the nCE signal is wired to the ChipSelect associated
> >> to bus address of the NAND
Le 13/02/2017 à 11:30, Boris Brezillon a écrit :
On Fri, 10 Feb 2017 15:01:10 +0100 (CET)
Christophe Leroy wrote:
On some hardware, the nCE signal is wired to the ChipSelect associated
to bus address of the NAND, so it is automatically driven during the
memory access and it is not managed by
On Fri, 10 Feb 2017 15:01:10 +0100 (CET)
Christophe Leroy wrote:
> On some hardware, the nCE signal is wired to the ChipSelect associated
> to bus address of the NAND, so it is automatically driven during the
> memory access and it is not managed by a GPIO.
Hm, I'm not sure how this can work, be
On 02/10/2017 03:01 PM, Christophe Leroy wrote:
> On some hardware,
Can you be more specific or is that confidential ? Anyway, that's just
my curiosity, what hardware is done like that.
> the nCE signal is wired to the ChipSelect associated
> to bus address of the NAND, so it is automatically dri
On some hardware, the nCE signal is wired to the ChipSelect associated
to bus address of the NAND, so it is automatically driven during the
memory access and it is not managed by a GPIO.
Signed-off-by: Christophe Leroy
---
drivers/mtd/nand/gpio.c | 18 --
1 file changed, 12 inser
10 matches
Mail list logo