Re: [PATCH] mtd: spi-nor: use 16-bit WRR command when QE is set on spansion flashes

Hi Tudor, On Wed, Jun 19, 2019 at 5:47 PM wrote: > On 06/11/2019 11:35 AM, Geert Uytterhoeven wrote: > > On Mon, Jun 10, 2019 at 8:24 AM wrote: > >> From: Tudor Ambarus > >> > >> SPI memory devices from different manufacturers have widely > >> different configurations for Status, Control and Co

Re: [PATCH] mtd: spi-nor: use 16-bit WRR command when QE is set on spansion flashes

Hi, Geert, On 06/11/2019 11:35 AM, Geert Uytterhoeven wrote: > Hi Tudor, > > On Mon, Jun 10, 2019 at 8:24 AM wrote: >> From: Tudor Ambarus >> >> SPI memory devices from different manufacturers have widely >> different configurations for Status, Control and Configuration >> registers. JEDEC 216C

[PATCH] mtd: spi-nor: use 16-bit WRR command when QE is set on spansion flashes

From: Tudor Ambarus SPI memory devices from different manufacturers have widely different configurations for Status, Control and Configuration registers. JEDEC 216C defines a new map for these common register bits and their functions, and describes how the individual bits may be accessed for a sp

Re: [PATCH] mtd: spi-nor: use 16-bit WRR command when QE is set on spansion flashes

Hi, On 10-Jun-19 11:54 AM, tudor.amba...@microchip.com wrote: > From: Tudor Ambarus > > SPI memory devices from different manufacturers have widely > different configurations for Status, Control and Configuration > registers. JEDEC 216C defines a new map for these common register > bits and thei

Re: [PATCH] mtd: spi-nor: use 16-bit WRR command when QE is set on spansion flashes

Hi Tudor, On Mon, Jun 10, 2019 at 8:24 AM wrote: > From: Tudor Ambarus > > SPI memory devices from different manufacturers have widely > different configurations for Status, Control and Configuration > registers. JEDEC 216C defines a new map for these common register > bits and their functions,

Re: [PATCH] mtd: spi-nor: use 16-bit WRR command when QE is set on spansion flashes

Hi Tudor, On 10/06/2019 08:24, tudor.amba...@microchip.com wrote: From: Tudor Ambarus SPI memory devices from different manufacturers have widely different configurations for Status, Control and Configuration registers. JEDEC 216C defines a new map for these common register bits and their func

[PATCH] mtd: spi-nor: use 16-bit WRR command when QE is set on spansion flashes

From: Tudor Ambarus SPI memory devices from different manufacturers have widely different configurations for Status, Control and Configuration registers. JEDEC 216C defines a new map for these common register bits and their functions, and describes how the individual bits may be accessed for a sp