On Wed, 23 Nov 2016, David Singleton wrote:
> --- /dev/null
> +++ b/arch/x86/platform/asr1k/asr1k_aer.c
> @@ -0,0 +1,165 @@
> +/*
> + * Cisco ASR1K platform PCIe AER support
Please move this into drivers/platform/x86/asrik/ or into a proper space in
drivers/pci/
This is pure driver space and has
From: Steve Shih
ASR1K FPGAs and ASICs are configured to raise SERR/PERR through PCIe AER.
When an error is raised, it is detected at the root complex, but it is not
detected by the AER driver. If the root complex bridge control register is
configured to forward secondary bus errors to the primar
ISCCTRLSTS_REG, ®32);
reg32 |= MISCCTRLSTS_DISABLE_EOI_MASK;
pci_write_config_dword(pdev, MISCCTRLSTS_REG, reg32);
-Steve
From bf52b18d6babf4d1ff79b6036369af9d5dc991be Mon Sep 17 00:00:00 2001
From: Steve Shih
Date: Mon, 10 Oct 2016 19:23:58 -0700
Subject: [PATCH] pcie: aer: aerdrv: PCIe AER
[+cc Po]
Hi Steve & David,
On Mon, Oct 17, 2016 at 09:51:06AM -0700, David Singleton wrote:
> From: Steve Shih
>
> ASR1K FPGAs and ASICs are configured to raise SERR/PERR through PCIe AER.
> When an error is raised, it is detected at the root complex, but it is not
> detected by the AER driver.
From: Steve Shih
ASR1K FPGAs and ASICs are configured to raise SERR/PERR through PCIe AER.
When an error is raised, it is detected at the root complex, but it is not
detected by the AER driver. If the root complex bridge control register is
configured to forward secondary bus errors to the primar
5 matches
Mail list logo
