Re: [PATCH] perf, x86: Widen Haswell OFFCORE mask

On Sat, Jul 12, 2014 at 2:06 AM, Andi Kleen wrote: > From: Andi Kleen > > Haswell supports more bits in the offcore_rsp_* MSRs than Sandy > Bridge. Previously the Haswell code was using the Sandy Bridge > extra register definitions, which prevented users from setting > all of these bits. This in

[PATCH] perf, x86: Widen Haswell OFFCORE mask

From: Andi Kleen Haswell supports more bits in the offcore_rsp_* MSRs than Sandy Bridge. Previously the Haswell code was using the Sandy Bridge extra register definitions, which prevented users from setting all of these bits. This in term did not allow to set some valid SNOOP_* bits, among others