Re: [PATCH] perf, x86: add Intel IvyBridge event scheduling constraints

2013-02-25 Thread yqzhang
when HTT is off A3H 08H CYCLE_ACTIVITY.CYCLES_L1D_PENDING - Cycles with pending L1 cache miss loads. SetCmask=8 to count cycle.PMC2 only Thanks a lot! -- View this message in context: http://linux-kernel.2935.n7.nabble.com/PATCH-perf-x86-add-Intel-IvyBridge-event-scheduling-constr

Re: [PATCH] perf, x86: add Intel IvyBridge event scheduling constraints

2013-02-21 Thread Stephane Eranian
On Wed, Feb 20, 2013 at 11:08 PM, Andi Kleen wrote: >> > Except for LDM_PENDING the CYCLE_ACTIVITY events have been also added to >> > Sandy Bridge. >> > So it should be also added there. >> > >> As far as I know and I double-checked the documentation I have, there >> is no CYCLE_ACTIVITY >> even

Re: [PATCH] perf, x86: add Intel IvyBridge event scheduling constraints

2013-02-20 Thread Andi Kleen
> > Except for LDM_PENDING the CYCLE_ACTIVITY events have been also added to > > Sandy Bridge. > > So it should be also added there. > > > As far as I know and I double-checked the documentation I have, there > is no CYCLE_ACTIVITY > event on SNB or SNB-EP. page 19-28 in the Jan 2013 SDM. It was

Re: [PATCH] perf, x86: add Intel IvyBridge event scheduling constraints

2013-02-20 Thread Stephane Eranian
On Wed, Feb 20, 2013 at 4:43 PM, Andi Kleen wrote: > On Wed, Feb 20, 2013 at 11:15:12AM +0100, Stephane Eranian wrote: >> Intel IvyBridge processor has different constraints compared >> to SandyBridge. Therefore it needs its own contraint table. >> This patch adds the constraint table. Without thi

Re: [PATCH] perf, x86: add Intel IvyBridge event scheduling constraints

2013-02-20 Thread Andi Kleen
On Wed, Feb 20, 2013 at 11:15:12AM +0100, Stephane Eranian wrote: > Intel IvyBridge processor has different constraints compared > to SandyBridge. Therefore it needs its own contraint table. > This patch adds the constraint table. Without this patch, > the events listed in the patch may not be sche

[PATCH] perf, x86: add Intel IvyBridge event scheduling constraints

2013-02-20 Thread Stephane Eranian
Intel IvyBridge processor has different constraints compared to SandyBridge. Therefore it needs its own contraint table. This patch adds the constraint table. Without this patch, the events listed in the patch may not be scheduled correctly and bogus counts may be collected. Signed-off-by: Stephan