On Thu, Sep 06, 2018 at 03:57:48PM +0200, Jiri Olsa wrote:
SNIP
> > looks like it would ;-) will check and repost
>
> new version attached.. Michael tested on several machines,
> but I couldn't find haswell with working tsx, to test
> that those events are displayed
>
> thanks,
> jirka
ping
j
On Tue, Aug 28, 2018 at 10:19:11AM +0200, Jiri Olsa wrote:
> On Tue, Aug 28, 2018 at 10:12:32AM +0200, Peter Zijlstra wrote:
> > On Mon, Aug 27, 2018 at 11:06:24AM +0200, Jiri Olsa wrote:
> > > +static __init struct attribute **get_hsw_events_attrs(bool *alloc)
> > > {
> > > + if (boot_cpu_has(X86
On Tue, Aug 28, 2018 at 10:12:32AM +0200, Peter Zijlstra wrote:
> On Mon, Aug 27, 2018 at 11:06:24AM +0200, Jiri Olsa wrote:
> > +static __init struct attribute **get_hsw_events_attrs(bool *alloc)
> > {
> > + if (boot_cpu_has(X86_FEATURE_RTM)) {
> > + *alloc = true;
> > + ret
On Mon, Aug 27, 2018 at 11:06:24AM +0200, Jiri Olsa wrote:
> +static __init struct attribute **get_hsw_events_attrs(bool *alloc)
> {
> + if (boot_cpu_has(X86_FEATURE_RTM)) {
> + *alloc = true;
> + return merge_attr(hsw_events_attrs, hsw_tsx_events_attrs);
> + }
> +
Memory events depends on PEBs support and access to LDLAT msr,
but we display them in /sys/devices/cpu/events even if the cpu
does not provide those, like for KVM guests.
That brings the false assumption that those events should
be available, while they fail event to open.
Separating the mem-* ev
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