Re: [PATCH] pinctrl/amd: poll InterruptEnable bits in enable_irq

2018-03-27 Thread Shah, Nehal-bakulchandra
Hi On 3/26/2018 2:42 PM, Linus Walleij wrote: > On Mon, Mar 12, 2018 at 5:45 PM, Daniel Kurtz wrote: > >> In certain cases interrupt enablement will be delayed relative to when >> the InterruptEnable bits are written. One example of this is when >> a GPIO's "debounce" logice is first enabled.

Re: [PATCH] pinctrl/amd: poll InterruptEnable bits in enable_irq

2018-03-26 Thread Linus Walleij
On Mon, Mar 12, 2018 at 5:45 PM, Daniel Kurtz wrote: > In certain cases interrupt enablement will be delayed relative to when > the InterruptEnable bits are written. One example of this is when > a GPIO's "debounce" logice is first enabled. After enabling debounce, > there is a 900 us "warm up"

[PATCH] pinctrl/amd: poll InterruptEnable bits in enable_irq

2018-03-12 Thread Daniel Kurtz
In certain cases interrupt enablement will be delayed relative to when the InterruptEnable bits are written. One example of this is when a GPIO's "debounce" logice is first enabled. After enabling debounce, there is a 900 us "warm up" period during which InterruptEnable[0] (bit 11) will read as 0