On Tue, 2018-01-09 at 16:32 +0100, Matthias Brugger wrote:
>
> On 12/25/2017 03:59 PM, sean.w...@mediatek.com wrote:
> > From: Sean Wang
> >
> > Since the offset for both registers, PWMDWIDTH and PWMTHRES, used to
> > control PWM4 or PWM5 are distinct from the other
On Tue, 2018-01-09 at 16:32 +0100, Matthias Brugger wrote:
>
> On 12/25/2017 03:59 PM, sean.w...@mediatek.com wrote:
> > From: Sean Wang
> >
> > Since the offset for both registers, PWMDWIDTH and PWMTHRES, used to
> > control PWM4 or PWM5 are distinct from the other PWMs, whose wrong
> >
On 12/25/2017 03:59 PM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Since the offset for both registers, PWMDWIDTH and PWMTHRES, used to
> control PWM4 or PWM5 are distinct from the other PWMs, whose wrong
> programming on PWM hardware causes waveform cannot be
On 12/25/2017 03:59 PM, sean.w...@mediatek.com wrote:
> From: Sean Wang
>
> Since the offset for both registers, PWMDWIDTH and PWMTHRES, used to
> control PWM4 or PWM5 are distinct from the other PWMs, whose wrong
> programming on PWM hardware causes waveform cannot be output as expected.
>
From: Sean Wang
Since the offset for both registers, PWMDWIDTH and PWMTHRES, used to
control PWM4 or PWM5 are distinct from the other PWMs, whose wrong
programming on PWM hardware causes waveform cannot be output as expected.
Thus, the patch adds the extra condition for
From: Sean Wang
Since the offset for both registers, PWMDWIDTH and PWMTHRES, used to
control PWM4 or PWM5 are distinct from the other PWMs, whose wrong
programming on PWM hardware causes waveform cannot be output as expected.
Thus, the patch adds the extra condition for fixing up the weird case
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