On Wed, 7 Aug 2019, Alexandre Ghiti wrote:
> And FYI my series and your patch are already in linux-next.
Yes, I agree with Christoph that it would be preferable not to break
randconfig/allyesconfig. So if you don't mind, could you respin the
RISC-V patch to drop the Sv48 portion, and simply
On Wed, 07 Aug 2019 08:12:30 PDT (-0700), Christoph Hellwig wrote:
On Wed, Aug 07, 2019 at 09:04:40AM +0200, Alexandre Ghiti wrote:
I took a look at how x86 deals with 5-level page table: it allows to handle
5-level and 4-level at runtime by folding the last page table level (cf
On Wed, Aug 07, 2019 at 09:04:40AM +0200, Alexandre Ghiti wrote:
> I took a look at how x86 deals with 5-level page table: it allows to handle
> 5-level and 4-level at runtime by folding the last page table level (cf
> Documentation/x86/x86_64/5level-paging.rst). So we might want to be able to
>
On 8/7/19 7:42 AM, Christoph Hellwig wrote:
On Tue, Aug 06, 2019 at 05:02:03PM -0700, Paul Walmsley wrote:
The rationale is to encourage others to start laying the groundwork for
future Sv48 support. The immediate trigger for it was Alex's mmap
randomization support patch series, which needs
On Tue, Aug 06, 2019 at 05:02:03PM -0700, Paul Walmsley wrote:
> The rationale is to encourage others to start laying the groundwork for
> future Sv48 support. The immediate trigger for it was Alex's mmap
> randomization support patch series, which needs to set some Kconfig
> options
On Fri, 2 Aug 2019, Christoph Hellwig wrote:
> On Fri, Jul 26, 2019 at 01:00:49PM -0700, Paul Walmsley wrote:
> >
> > The RISC-V specifications currently define three virtual memory
> > translation systems: Sv32, Sv39, and Sv48. Sv32 is currently specific
> > to 32-bit systems; Sv39 and Sv48
On Fri, Jul 26, 2019 at 01:00:49PM -0700, Paul Walmsley wrote:
>
> The RISC-V specifications currently define three virtual memory
> translation systems: Sv32, Sv39, and Sv48. Sv32 is currently specific
> to 32-bit systems; Sv39 and Sv48 are currently specific to 64-bit
> systems. The current
On Thu, Aug 1, 2019 at 3:37 AM Paul Walmsley wrote:
>
> On Sun, 28 Jul 2019, Bin Meng wrote:
>
> > The spec does not mention 40-bit physical addresses, but 56-bit.
>
> Thanks, agreed. Updated patch below
>
>
> - Paul
>
> From: Paul Walmsley
> Date: Fri, 26 Jul 2019 10:21:11 -0700
> Subject:
On Sun, 28 Jul 2019, Bin Meng wrote:
> The spec does not mention 40-bit physical addresses, but 56-bit.
Thanks, agreed. Updated patch below
- Paul
From: Paul Walmsley
Date: Fri, 26 Jul 2019 10:21:11 -0700
Subject: [PATCH v2] riscv: kbuild: add virtual memory system selection
The RISC-V
On Sat, Jul 27, 2019 at 4:00 AM Paul Walmsley wrote:
>
>
> The RISC-V specifications currently define three virtual memory
> translation systems: Sv32, Sv39, and Sv48. Sv32 is currently specific
> to 32-bit systems; Sv39 and Sv48 are currently specific to 64-bit
> systems. The current kernel
The RISC-V specifications currently define three virtual memory
translation systems: Sv32, Sv39, and Sv48. Sv32 is currently specific
to 32-bit systems; Sv39 and Sv48 are currently specific to 64-bit
systems. The current kernel only supports Sv32 and Sv39, but we'd
like to start preparing for
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