On Tuesday, January 23, 2018 10:57:51 AM CET davidwang wrote:
> For Centaur CPU, the ucode will make sure that each cpu core can keep cache
> coherency with each other when the CPU core entering to any C State. So the
> cache
> flush operations when enter C3 is not necessary and will cause large C
For Centaur CPU, the ucode will make sure that each cpu core can keep cache
coherency with each other when the CPU core entering to any C State. So the
cache
flush operations when enter C3 is not necessary and will cause large C3
enter/exit
latency.
And the bus master disable operation when CPU c
; Qiyuan Wang(BJ-RD) ; Benjamin
Pan
主题: 答复: [PATCH] x86/acpi/cstate delete some unuseful operations
Dear Rafael,
Sorry to miss this mail.
I understood that it was not necessary to disable bus master arbitration on C3
entry for Centaur CPUs, which is why you clear bm_control, right?
[Comment b
nix.de; mi...@redhat.com; h...@zytor.com; mi...@kernel.org;
x...@kernel.org; linux...@vger.kernel.org; linux-kernel@vger.kernel.org; Bruce
Chang (VAS) ; Cooper Yan(BJ-RD)
; Qiyuan Wang(BJ-RD) ; Benjamin
Pan
主题: Re: [PATCH] x86/acpi/cstate delete some unuseful operations
On Friday, December
On Friday, December 22, 2017 12:55:04 PM CET TimGuo wrote:
> Unuseful cache flush operations which will be executed by ucode when entering
> C3 will
> cause larger C3 enter latency. And the bus master disable operation is not
> need for
> centaur platforms.
My attempts to make some sense of the
Unuseful cache flush operations which will be executed by ucode when entering
C3 will
cause larger C3 enter latency. And the bus master disable operation is not need
for
centaur platforms.
Signed-off-by: TimGuo
---
arch/x86/kernel/acpi/cstate.c | 12
1 file changed, 12 insertions(
6 matches
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