On Thu, Mar 21, 2019 at 09:15:22PM +, Phillips, Kim wrote:
> From: Kim Phillips
>
> Family 17h differs from prior families by:
> - not supporting an L2 cache miss event
> - having re-enumerated PMC counters for:
>- L2 cache references
>- front & back end stalled cycles
>
> So we ad
From: Kim Phillips
Family 17h differs from prior families by:
- not supporting an L2 cache miss event
- having re-enumerated PMC counters for:
- L2 cache references
- front & back end stalled cycles
So we add a new amd_f17h_perfmon_event_map so that the generic
perf event names will reso
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