nel.org
> Subject: Re: [PATCH] x86/mce/AMD: Fix partial SMCA bank init when CPU 0 !=
> thread 0
>
> On Wed, Jun 28, 2017 at 1:58 PM, Ghannam, Yazen
> wrote:
> >> With my patch applied, I see entries like l3_cache under hardware
> >> thread 0's directory (it&#
On Wed, Jun 28, 2017 at 1:58 PM, Ghannam, Yazen wrote:
>> With my patch applied, I see entries like l3_cache under hardware thread 0's
>> directory (it's shifted to CPU 1, so machinecheck1).
>> Without my patch, only machinecheck0 has anything interesting in it
>> (insn_fetch, l2_cache etc.) becau
On Wed, Jun 28, 2017 at 06:51:08PM +, Ghannam, Yazen wrote:
> The non-core MCA banks are only visible to a "master thread" on each Die. The
> master thread is the first one on the Die. Since we have the same banks on
> each
> Die we only need to read them once, and I assumed that CPU0 would al
nel.org
> Subject: Re: [PATCH] x86/mce/AMD: Fix partial SMCA bank init when CPU 0 !=
> thread 0
>
> On Wed, Jun 28, 2017 at 1:00 PM, Ghannam, Yazen
> wrote:
> >> -Original Message-
> >> From: themo...@gmail.com [mailto:themo...@gmail.com] On Behalf Of
> &
; linux-kernel@vger.kernel.org;
>> t...@linutronix.de; Ghannam, Yazen ;
>> x...@kernel.org
>> Subject: Re: [PATCH] x86/mce/AMD: Fix partial SMCA bank init when CPU 0 !=
>> thread 0
>>
>> On Wed, Jun 28, 2017 at 4:22 AM, Borislav Petkov wrote:
>> > On Tue, Ju
> -Original Message-
> From: Borislav Petkov [mailto:b...@suse.de]
> Sent: Wednesday, June 28, 2017 2:17 PM
> To: Jack Miller ; Ghannam, Yazen
>
> Cc: linux-kernel@vger.kernel.org; t...@linutronix.de; x...@kernel.org
> Subject: Re: [PATCH] x86/mce/AMD: Fix partial SM
On Wed, Jun 28, 2017 at 12:44:17PM -0500, Jack Miller wrote:
> SwitchBSP() is part of the UEFI MPServices Protocol which I believe is
> an extension but it is supported by all of the firmwares I've tested
> on.
Damn, that ubiquitous firmware. One day the kernel will be just a
userspace process to
kernel.org
> Subject: Re: [PATCH] x86/mce/AMD: Fix partial SMCA bank init when CPU 0 !=
> thread 0
>
> On Wed, Jun 28, 2017 at 4:22 AM, Borislav Petkov wrote:
> > On Tue, Jun 27, 2017 at 07:06:30PM -0500, Jack Miller wrote:
> >> After a call to firmware SwitchBSP(),
>
On Wed, Jun 28, 2017 at 4:22 AM, Borislav Petkov wrote:
> On Tue, Jun 27, 2017 at 07:06:30PM -0500, Jack Miller wrote:
>> After a call to firmware SwitchBSP(),
>
> What is that and who does that?
SwitchBSP() is part of the UEFI MPServices Protocol which I believe is
an extension but it is support
On Tue, Jun 27, 2017 at 07:06:30PM -0500, Jack Miller wrote:
> After a call to firmware SwitchBSP(),
What is that and who does that?
> Linux can be booted with a thread
> that isn't the first in the system. That thread automatically becomes
> CPU 0.
Btw, you should be seeing other explosions too
After a call to firmware SwitchBSP(), Linux can be booted with a thread
that isn't the first in the system. That thread automatically becomes
CPU 0.
Currently get_smca_bank_info() queries CPU 0's MCA types, but if CPU 0
!= hardware thread 0, it will get an incomplete list of MCA types in
smca_bank
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