On Thu, Mar 14, 2013 at 12:11:18PM -0400, Boris Ostrovsky wrote:
> Currently number of error reporting register banks is hardcoded to
> 6 on AMD processors. This may break in virtualized scenarios when
> a hypervisor prefers to report fewer banks that the physical HW
> provides.
>
> Since number o
Currently number of error reporting register banks is hardcoded to
6 on AMD processors. This may break in virtualized scenarios when
a hypervisor prefers to report fewer banks that the physical HW
provides.
Since number of supported banks is reported in MSR_IA32_MCG_CAP[7:0]
that's what we should
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