On Thu, 2015-07-23 at 10:40 -0700, Dan Williams wrote:
> On Thu, Jul 23, 2015 at 10:33 AM, Toshi Kani wrote:
> > During power failure, Asynchronous DRAM Refresh (ADR) flushes
> > the write buffer in memory controllers into NVDIMM, but does not
> > flush processor caches. While the kernel and appl
On Thu, Jul 23, 2015 at 10:33 AM, Toshi Kani wrote:
> During power failure, Asynchronous DRAM Refresh (ADR) flushes
> the write buffer in memory controllers into NVDIMM, but does not
> flush processor caches. While the kernel and application code
> need to take care of processor cache flush, they
During power failure, Asynchronous DRAM Refresh (ADR) flushes
the write buffer in memory controllers into NVDIMM, but does not
flush processor caches. While the kernel and application code
need to take care of processor cache flush, they may not be able
to do so during panic or reboot.
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