Hi Reinette,
On 11/18/20 4:18 PM, Reinette Chatre wrote:
> Hi Babu,
>
> On 11/6/2020 12:14 PM, Babu Moger wrote:
>> When the AMD QoS feature CDP(code and data prioritization) is enabled
>> or disabled, the CDP bit in MSR _0C81 is written on one of the
>> cpus in L3 domain(core complex). That
Hi Babu,
On 11/6/2020 12:14 PM, Babu Moger wrote:
When the AMD QoS feature CDP(code and data prioritization) is enabled
or disabled, the CDP bit in MSR _0C81 is written on one of the
cpus in L3 domain(core complex). That is not correct. The CDP bit needs
to be updated all the logical cpus in
When the AMD QoS feature CDP(code and data prioritization) is enabled
or disabled, the CDP bit in MSR _0C81 is written on one of the
cpus in L3 domain(core complex). That is not correct. The CDP bit needs
to be updated all the logical cpus in the domain.
This was not spelled out clearly in the
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