Re: [PATCH] x86/tsc: mark tsc reliable on CoffeeLake

2019-04-11 Thread You-Sheng Yang
On 2019/4/8 8:03 PM, Thomas Gleixner wrote: > On Mon, 8 Apr 2019, You-Sheng Yang wrote: >> +/* >> + * On Intel CoffeeLake, tsc may be marked unstable unexpectedly after >> + * entering PC10. >> + */ >> +if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && >> +

Re: [PATCH] x86/tsc: mark tsc reliable on CoffeeLake

2019-04-10 Thread You-Sheng Yang
On 2019/4/8 8:03 PM, Thomas Gleixner wrote: > On Mon, 8 Apr 2019, You-Sheng Yang wrote: > >> From: You-Sheng Yang >> >> On Intel CoffeeLake it's observed tsc is always marked unstable >> unexpectedly after entering idle state Package C10(PC10), and then clock >> source is switched to hpet. This

Re: [PATCH] x86/tsc: mark tsc reliable on CoffeeLake

2019-04-08 Thread Thomas Gleixner
On Mon, 8 Apr 2019, You-Sheng Yang wrote: > From: You-Sheng Yang > > On Intel CoffeeLake it's observed tsc is always marked unstable > unexpectedly after entering idle state Package C10(PC10), and then clock > source is switched to hpet. This patch marks tsc as reliable when CPUID > matches

[PATCH] x86/tsc: mark tsc reliable on CoffeeLake

2019-04-08 Thread You-Sheng Yang
From: You-Sheng Yang On Intel CoffeeLake it's observed tsc is always marked unstable unexpectedly after entering idle state Package C10(PC10), and then clock source is switched to hpet. This patch marks tsc as reliable when CPUID matches CoffeeLake. Link: