I committed my own patch yesterday; at this point it would be most helpful if
you could test it out to make sure it works as it should...
Bryan O'Donoghue wrote:
>On 20/04/13 00:13, H. Peter Anvin wrote:
>> On 04/19/2013 02:44 PM, Bryan O'Donoghue wrote:
>>> On 19/04/13 22:25, Borislav Petkov w
Architectural MSRs associated with microcode are for P6 or higher.
Add a check to early microcode to detect < P6.
Without a check for < P6 - we end up reading from unimplemented MSRs
on Pentium.
Thanks to Borislav Petkov for suggestion on where to intercept the P5
resulting in fewer cycles and le
On 20/04/13 00:13, H. Peter Anvin wrote:
On 04/19/2013 02:44 PM, Bryan O'Donoghue wrote:
On 19/04/13 22:25, Borislav Petkov wrote:
On Fri, Apr 19, 2013 at 10:55:15PM +0200, Borislav Petkov wrote:
Just filter out P5 and earlier. The code already does that for CPUs
which don't have CPUID.
Actu
On 04/19/2013 02:44 PM, Bryan O'Donoghue wrote:
> On 19/04/13 22:25, Borislav Petkov wrote:
>> On Fri, Apr 19, 2013 at 10:55:15PM +0200, Borislav Petkov wrote:
>>> Just filter out P5 and earlier. The code already does that for CPUs
>>> which don't have CPUID.
>>
>> Actually, an alternative - more p
On 04/19/2013 02:44 PM, Bryan O'Donoghue wrote:
> On 19/04/13 22:25, Borislav Petkov wrote:
>> On Fri, Apr 19, 2013 at 10:55:15PM +0200, Borislav Petkov wrote:
>>> Just filter out P5 and earlier. The code already does that for CPUs
>>> which don't have CPUID.
>>
>> Actually, an alternative - more p
On 19/04/13 22:25, Borislav Petkov wrote:
On Fri, Apr 19, 2013 at 10:55:15PM +0200, Borislav Petkov wrote:
Just filter out P5 and earlier. The code already does that for CPUs
which don't have CPUID.
Actually, an alternative - more practical albeit not very accurate
More practical ? Hmm - the
On Fri, Apr 19, 2013 at 10:55:15PM +0200, Borislav Petkov wrote:
> Just filter out P5 and earlier. The code already does that for CPUs
> which don't have CPUID.
Actually, an alternative - more practical albeit not very accurate
solution would be to check for which families Intel delivers microcode
On Fri, Apr 19, 2013 at 09:35:18PM +0100, Bryan O'Donoghue wrote:
> Just returning X86_VENDOR_UNKNOWN - won't fix the bug though - after
> all MSR_IA32_UCODE_REV is also x86_family() >= 6
What are you talking about?
If you return X86_VENDOR_UNKNOWN from x86_vendor(),
load_ucode_intel_bsp() and lo
On 19/04/13 20:11, Borislav Petkov wrote:
On Fri, Apr 19, 2013 at 06:23:03PM +0100, Bryan O'Donoghue wrote:
Architectural MSRs associated with microcode are for P6 or higher.
Add a check to early microcode to detect< P6.
Without a check for< P6 - we end up reading from unimplemented MSRs
on P
On Fri, Apr 19, 2013 at 06:23:03PM +0100, Bryan O'Donoghue wrote:
> Architectural MSRs associated with microcode are for P6 or higher.
> Add a check to early microcode to detect < P6.
>
> Without a check for < P6 - we end up reading from unimplemented MSRs
> on Pentium.
Is this something you're a
Architectural MSRs associated with microcode are for P6 or higher.
Add a check to early microcode to detect < P6.
Without a check for < P6 - we end up reading from unimplemented MSRs
on Pentium.
Signed-off-by: Bryan O'Donoghue
---
arch/x86/kernel/microcode_intel_early.c | 21 -
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