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Subject: Re: [PATCH] x86: Intel Cache Allocation Technology support
On Wed, 19 Nov 2014, Vikas Shivappa wrote:
> +/* maximum possible cbm length */
> +#define MAX_CBM_LENGTH 32
> +
> +#define IA32_CBMMAX_MASK(x)(0x & (~((u64)(1 << x)
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Subject: Re: [PATCH] x86: Intel Cache Allocation Technology support
On Wed, 19 Nov 2014, Vikas Shivappa wrote:
+/* maximum possible cbm length */
+#define MAX_CBM_LENGTH 32
+
+#define IA32_CBMMAX_MASK(x)(0x (~((u64)(1 x) - 1)))
Unused define
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Subject: Re: [PATCH] x86: Intel Cache Allocation Technology support
On Wed, 19 Nov 2014, Vikas Shivappa wrote:
> +/* maximum possible cbm length */
> +#define MAX_CBM_LENGTH 32
> +
> +#define IA32_CBMMAX_MASK(x)(0x & (~((u64)(1 << x)
...@infradead.org
Subject: Re: [PATCH] x86: Intel Cache Allocation Technology support
On Fri, 21 Nov 2014, Vikas Shivappa wrote:
> On Fri, 21 Nov 2014, Thomas Gleixner wrote:
> > On Wed, 19 Nov 2014, Vikas Shivappa wrote:
> > > + rdmsr(IA32_PQR_ASSOC, l, h);
> >
> > Why on e
...@infradead.org
Subject: Re: [PATCH] x86: Intel Cache Allocation Technology support
On Fri, 21 Nov 2014, Vikas Shivappa wrote:
On Fri, 21 Nov 2014, Thomas Gleixner wrote:
On Wed, 19 Nov 2014, Vikas Shivappa wrote:
+ rdmsr(IA32_PQR_ASSOC, l, h);
Why on earth do we want to read an MSR on every context
...@infradead.org
Subject: Re: [PATCH] x86: Intel Cache Allocation Technology support
On Wed, 19 Nov 2014, Vikas Shivappa wrote:
+/* maximum possible cbm length */
+#define MAX_CBM_LENGTH 32
+
+#define IA32_CBMMAX_MASK(x)(0x (~((u64)(1 x) - 1)))
Unused define
On Fri, 21 Nov 2014, Vikas Shivappa wrote:
> On Fri, 21 Nov 2014, Thomas Gleixner wrote:
> > On Wed, 19 Nov 2014, Vikas Shivappa wrote:
> > > + rdmsr(IA32_PQR_ASSOC, l, h);
> >
> > Why on earth do we want to read an MSR on every context switch? What's
> > wrong with having
> >
> >
On Sun, 23 Nov 2014, Matt Fleming wrote:
> Something like this?
>
> first_bit = find_next_bit(map, nr_bits, -1);
> zero_bit = find_next_zero_bit(map, nr_bits, first_bit);
>
> if (find_next_bit(map, nr_bits, zero_bit) < nr_bits)
> return -EINVAL; /* non-contiguous
On Fri, 21 Nov, at 03:19:52PM, Thomas Gleixner wrote:
> > + barrier();
> > + cqe_genable = true;
>
> What's the exact point of that barrier?
Yes, this definitely needs documenting. Vikas?
> > +
> > +/*
> > + * Tests if only contiguous bits are set.
> > + */
> > +
> >
On Fri, 21 Nov, at 03:19:52PM, Thomas Gleixner wrote:
+ barrier();
+ cqe_genable = true;
What's the exact point of that barrier?
Yes, this definitely needs documenting. Vikas?
+
+/*
+ * Tests if only contiguous bits are set.
+ */
+
+static inline bool
On Sun, 23 Nov 2014, Matt Fleming wrote:
Something like this?
first_bit = find_next_bit(map, nr_bits, -1);
zero_bit = find_next_zero_bit(map, nr_bits, first_bit);
if (find_next_bit(map, nr_bits, zero_bit) nr_bits)
return -EINVAL; /* non-contiguous bits */
On Fri, 21 Nov 2014, Vikas Shivappa wrote:
On Fri, 21 Nov 2014, Thomas Gleixner wrote:
On Wed, 19 Nov 2014, Vikas Shivappa wrote:
+ rdmsr(IA32_PQR_ASSOC, l, h);
Why on earth do we want to read an MSR on every context switch? What's
wrong with having
DEFINE_PER_CPU(u64,
On Fri, 21 Nov 2014, Thomas Gleixner wrote:
On Fri, 21 Nov 2014, Dave Hansen wrote:
On 11/19/2014 05:05 PM, Vikas Shivappa wrote:
+ /*
+* Hard code the checks and values for HSW SKUs.
+* Unfortunately! have to check against only these brand name strings.
+*/
+
Correcting email address for Matt.
On Wed, 19 Nov 2014, Vikas Shivappa wrote:
What is Cache Allocation Technology ( CAT )
---
Cache Allocation Technology provides a way for the Software (OS/VMM) to
restrict cache allocation to a defined 'subset' of
On Fri, 21 Nov 2014, Borislav Petkov wrote:
On Fri, Nov 21, 2014 at 12:00:27PM -0800, Vikas Shivappa wrote:
+char hsw_brandstrs[5][64] = {
+ "Intel(R) Xeon(R) CPU E5-2658 v3 @ 2.20GHz",
+ "Intel(R) Xeon(R) CPU E5-2648L v3 @ 1.80GHz",
+
On Fri, 21 Nov 2014, Dave Hansen wrote:
> On 11/19/2014 05:05 PM, Vikas Shivappa wrote:
> > + /*
> > +* Hard code the checks and values for HSW SKUs.
> > +* Unfortunately! have to check against only these brand name strings.
> > +*/
> > +
> > + for (i = 0; i < 5; i++)
> > +
On 11/19/2014 05:05 PM, Vikas Shivappa wrote:
> + /*
> + * Hard code the checks and values for HSW SKUs.
> + * Unfortunately! have to check against only these brand name strings.
> + */
> +
> + for (i = 0; i < 5; i++)
> + if (!strcmp(hsw_brandstrs[i],
On Fri, Nov 21, 2014 at 12:00:27PM -0800, Vikas Shivappa wrote:
> >>+char hsw_brandstrs[5][64] = {
> >>+ "Intel(R) Xeon(R) CPU E5-2658 v3 @ 2.20GHz",
> >>+ "Intel(R) Xeon(R) CPU E5-2648L v3 @ 1.80GHz",
> >>+ "Intel(R) Xeon(R) CPU
On Fri, 21 Nov 2014, Thomas Gleixner wrote:
On Wed, 19 Nov 2014, Vikas Shivappa wrote:
+/* maximum possible cbm length */
+#define MAX_CBM_LENGTH 32
+
+#define IA32_CBMMAX_MASK(x)(0x & (~((u64)(1 << x) - 1)))
Unused define.
Will remove , is there any
On Wed, 19 Nov 2014, Vikas Shivappa wrote:
> +/* maximum possible cbm length */
> +#define MAX_CBM_LENGTH 32
> +
> +#define IA32_CBMMAX_MASK(x)(0x & (~((u64)(1 << x) - 1)))
Unused define.
> +
> +#define IA32_CBM_MASK 0x
On Wed, 19 Nov 2014, Vikas Shivappa wrote:
+/* maximum possible cbm length */
+#define MAX_CBM_LENGTH 32
+
+#define IA32_CBMMAX_MASK(x)(0x (~((u64)(1 x) - 1)))
Unused define.
+
+#define IA32_CBM_MASK 0x
(~0U) ?
@@
On Fri, 21 Nov 2014, Thomas Gleixner wrote:
On Wed, 19 Nov 2014, Vikas Shivappa wrote:
+/* maximum possible cbm length */
+#define MAX_CBM_LENGTH 32
+
+#define IA32_CBMMAX_MASK(x)(0x (~((u64)(1 x) - 1)))
Unused define.
Will remove , is there any
On Fri, Nov 21, 2014 at 12:00:27PM -0800, Vikas Shivappa wrote:
+char hsw_brandstrs[5][64] = {
+ Intel(R) Xeon(R) CPU E5-2658 v3 @ 2.20GHz,
+ Intel(R) Xeon(R) CPU E5-2648L v3 @ 1.80GHz,
+ Intel(R) Xeon(R) CPU E5-2628L v3 @ 2.00GHz,
On 11/19/2014 05:05 PM, Vikas Shivappa wrote:
+ /*
+ * Hard code the checks and values for HSW SKUs.
+ * Unfortunately! have to check against only these brand name strings.
+ */
+
+ for (i = 0; i 5; i++)
+ if (!strcmp(hsw_brandstrs[i], c-x86_model_id)) {
On Fri, 21 Nov 2014, Dave Hansen wrote:
On 11/19/2014 05:05 PM, Vikas Shivappa wrote:
+ /*
+* Hard code the checks and values for HSW SKUs.
+* Unfortunately! have to check against only these brand name strings.
+*/
+
+ for (i = 0; i 5; i++)
+ if
On Fri, 21 Nov 2014, Borislav Petkov wrote:
On Fri, Nov 21, 2014 at 12:00:27PM -0800, Vikas Shivappa wrote:
+char hsw_brandstrs[5][64] = {
+ Intel(R) Xeon(R) CPU E5-2658 v3 @ 2.20GHz,
+ Intel(R) Xeon(R) CPU E5-2648L v3 @ 1.80GHz,
+
Correcting email address for Matt.
On Wed, 19 Nov 2014, Vikas Shivappa wrote:
What is Cache Allocation Technology ( CAT )
---
Cache Allocation Technology provides a way for the Software (OS/VMM) to
restrict cache allocation to a defined 'subset' of
On Fri, 21 Nov 2014, Thomas Gleixner wrote:
On Fri, 21 Nov 2014, Dave Hansen wrote:
On 11/19/2014 05:05 PM, Vikas Shivappa wrote:
+ /*
+* Hard code the checks and values for HSW SKUs.
+* Unfortunately! have to check against only these brand name strings.
+*/
+
What is Cache Allocation Technology ( CAT )
---
Cache Allocation Technology provides a way for the Software (OS/VMM) to
restrict cache allocation to a defined 'subset' of cache which may be
overlapping with other 'subsets'. This feature is used when
What is Cache Allocation Technology ( CAT )
---
Cache Allocation Technology provides a way for the Software (OS/VMM) to
restrict cache allocation to a defined 'subset' of cache which may be
overlapping with other 'subsets'. This feature is used when
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