Re: [PATCH] x86: serialize LVTT and TSC_DEADLINE write

2015-09-09 Thread Thomas Gleixner
Andi, On Tue, 8 Sep 2015, Andi Kleen wrote: > > Hmm, I didn't mean mfence can't serialize the instructions. For a true > > IO, a serialization can't guarantee device finishes the IO, we generally > > read some safe IO registers to wait IO finish. I completely don't know > > if this case fits here

Re: [PATCH] x86: serialize LVTT and TSC_DEADLINE write

2015-09-08 Thread Shaohua Li
9e808d05765 Mon Sep 17 00:00:00 2001 Message-Id: From: Shaohua Li Date: Thu, 30 Jul 2015 16:24:43 -0700 Subject: [PATCH] x86: serialize LVTT and TSC_DEADLINE write We saw a strange issue with local APIC timer. Some random CPU doesn't receive any local APIC timer interrupt, which causes dif

Re: [PATCH] x86: serialize LVTT and TSC_DEADLINE write

2015-09-08 Thread Andi Kleen
> Hmm, I didn't mean mfence can't serialize the instructions. For a true > IO, a serialization can't guarantee device finishes the IO, we generally > read some safe IO registers to wait IO finish. I completely don't know > if this case fits here though. Sorry for the late answer. We (Intel) analyz

Re: [PATCH] x86: serialize LVTT and TSC_DEADLINE write

2015-08-05 Thread Shaohua Li
On Wed, Aug 05, 2015 at 10:44:24AM +0200, Ingo Molnar wrote: > > * Shaohua Li wrote: > > > On Sun, Aug 02, 2015 at 09:41:08PM +0200, Thomas Gleixner wrote: > > > On Sun, 2 Aug 2015, Shaohua Li wrote: > > > > > > > On Sat, Aug 01, 2015 at 12:10:41PM +0200, Thomas Gleixner wrote: > > > > > On Fri

Re: [PATCH] x86: serialize LVTT and TSC_DEADLINE write

2015-08-05 Thread Ingo Molnar
* Shaohua Li wrote: > On Sun, Aug 02, 2015 at 09:41:08PM +0200, Thomas Gleixner wrote: > > On Sun, 2 Aug 2015, Shaohua Li wrote: > > > > > On Sat, Aug 01, 2015 at 12:10:41PM +0200, Thomas Gleixner wrote: > > > > On Fri, 31 Jul 2015, Shaohua Li wrote: > > > > > @@ -336,6 +336,22 @@ static void _

Re: [PATCH] x86: serialize LVTT and TSC_DEADLINE write

2015-08-03 Thread Shaohua Li
On Sun, Aug 02, 2015 at 09:41:08PM +0200, Thomas Gleixner wrote: > On Sun, 2 Aug 2015, Shaohua Li wrote: > > > On Sat, Aug 01, 2015 at 12:10:41PM +0200, Thomas Gleixner wrote: > > > On Fri, 31 Jul 2015, Shaohua Li wrote: > > > > @@ -336,6 +336,22 @@ static void __setup_APIC_LVTT(unsigned int clock

Re: [PATCH] x86: serialize LVTT and TSC_DEADLINE write

2015-08-02 Thread Thomas Gleixner
On Sun, 2 Aug 2015, Shaohua Li wrote: > On Sat, Aug 01, 2015 at 12:10:41PM +0200, Thomas Gleixner wrote: > > On Fri, 31 Jul 2015, Shaohua Li wrote: > > > @@ -336,6 +336,22 @@ static void __setup_APIC_LVTT(unsigned int clocks, > > > int oneshot, int irqen) > > > apic_write(APIC_LVTT, lvtt_value)

Re: [PATCH] x86: serialize LVTT and TSC_DEADLINE write

2015-08-02 Thread Shaohua Li
On Sat, Aug 01, 2015 at 12:10:41PM +0200, Thomas Gleixner wrote: > On Fri, 31 Jul 2015, Shaohua Li wrote: > > @@ -336,6 +336,22 @@ static void __setup_APIC_LVTT(unsigned int clocks, int > > oneshot, int irqen) > > apic_write(APIC_LVTT, lvtt_value); > > > > if (lvtt_value & APIC_LVT_TIMER

Re: [PATCH] x86: serialize LVTT and TSC_DEADLINE write

2015-08-01 Thread Thomas Gleixner
On Fri, 31 Jul 2015, Shaohua Li wrote: > @@ -336,6 +336,22 @@ static void __setup_APIC_LVTT(unsigned int clocks, int > oneshot, int irqen) > apic_write(APIC_LVTT, lvtt_value); > > if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { > + u64 msr; > + > + /* > +

[PATCH] x86: serialize LVTT and TSC_DEADLINE write

2015-07-31 Thread Shaohua Li
We saw a strange issue with local APIC timer. Some random CPU doesn't receive any local APIC timer interrupt, which causes different issues. The cpu uses TSC-Deadline mode for local APIC timer and APIC is in xAPIC mode. When this happens, manually writing TSC_DEADLINE MSR can trigger interrupt agai