On Thu, May 31, 2007 at 07:29:43AM -0600, Eric W. Biederman wrote:
> Andi Kleen <[EMAIL PROTECTED]> writes:
>
> > On Thursday 31 May 2007 13:34:21 Eric W. Biederman wrote:
> >>
> >> On x86_64 kernel, level triggered irq migration gets initiated in the
> >> context
> >> of that interrupt(after ex
looks good to me:
Acked-by: Ingo Molnar <[EMAIL PROTECTED]>
with a few minor style nits:
> +static int io_apic_level_ack_pending(unsigned int irq)
> +{
> + struct irq_pin_list *entry;
> + unsigned long flags;
> + int pending = 0;
> + spin_lock_irqsave(&ioapic_lock, flags);
ne
Andi Kleen <[EMAIL PROTECTED]> writes:
> On Thursday 31 May 2007 13:34:21 Eric W. Biederman wrote:
>>
>> On x86_64 kernel, level triggered irq migration gets initiated in the context
>> of that interrupt(after executing the irq handler) and following steps are
>> followed to do the irq migration.
On Thursday 31 May 2007 13:34:21 Eric W. Biederman wrote:
>
> On x86_64 kernel, level triggered irq migration gets initiated in the context
> of that interrupt(after executing the irq handler) and following steps are
> followed to do the irq migration.
What's the confidence level in the patch? Is
On x86_64 kernel, level triggered irq migration gets initiated in the context
of that interrupt(after executing the irq handler) and following steps are
followed to do the irq migration.
1. mask IOAPIC RTE entry; // write to IOAPIC RTE
2. EOI; // processor EOI write
3. r
5 matches
Mail list logo
