Pavel Machek wrote:
> Hi!
>
>> v3->v2, fixed the issues Matthew Wilcox raised.
>>
>> PCI Express ASPM defines a protocol for PCI Express components in the D0
>> state to reduce Link power by placing their Links into a low power state
>> and instructing the other end of the Link to do likewise.
Pavel Machek wrote:
Hi!
v3-v2, fixed the issues Matthew Wilcox raised.
PCI Express ASPM defines a protocol for PCI Express components in the D0
state to reduce Link power by placing their Links into a low power state
and instructing the other end of the Link to do likewise. This
>
>
>Hi!
>
>> v3->v2, fixed the issues Matthew Wilcox raised.
>>
>> PCI Express ASPM defines a protocol for PCI Express components in the
D0
>> state to reduce Link power by placing their Links into a low power
state
>> and instructing the other end of the Link to do likewise. This
>> capability
Hi!
> v3->v2, fixed the issues Matthew Wilcox raised.
>
> PCI Express ASPM defines a protocol for PCI Express components in the D0
> state to reduce Link power by placing their Links into a low power state
> and instructing the other end of the Link to do likewise. This
> capability allows
Hi!
v3-v2, fixed the issues Matthew Wilcox raised.
PCI Express ASPM defines a protocol for PCI Express components in the D0
state to reduce Link power by placing their Links into a low power state
and instructing the other end of the Link to do likewise. This
capability allows
Hi!
v3-v2, fixed the issues Matthew Wilcox raised.
PCI Express ASPM defines a protocol for PCI Express components in the
D0
state to reduce Link power by placing their Links into a low power
state
and instructing the other end of the Link to do likewise. This
capability allows
On Wed, 2008-01-23 at 10:26 -0800, Greg KH wrote:
> On Wed, Jan 23, 2008 at 10:20:54AM +0800, Shaohua Li wrote:
> >
> > On Tue, 2008-01-22 at 14:58 -0800, Greg KH wrote:
> > > On Fri, Jan 18, 2008 at 09:56:28AM +0800, Shaohua Li wrote:
> > > > v3->v2, fixed the issues Matthew Wilcox raised.
> >
On Wed, Jan 23, 2008 at 10:20:54AM +0800, Shaohua Li wrote:
>
> On Tue, 2008-01-22 at 14:58 -0800, Greg KH wrote:
> > On Fri, Jan 18, 2008 at 09:56:28AM +0800, Shaohua Li wrote:
> > > v3->v2, fixed the issues Matthew Wilcox raised.
> > >
> > > PCI Express ASPM defines a protocol for PCI Express
On Wed, Jan 23, 2008 at 10:20:54AM +0800, Shaohua Li wrote:
On Tue, 2008-01-22 at 14:58 -0800, Greg KH wrote:
On Fri, Jan 18, 2008 at 09:56:28AM +0800, Shaohua Li wrote:
v3-v2, fixed the issues Matthew Wilcox raised.
PCI Express ASPM defines a protocol for PCI Express components in
On Wed, 2008-01-23 at 10:26 -0800, Greg KH wrote:
On Wed, Jan 23, 2008 at 10:20:54AM +0800, Shaohua Li wrote:
On Tue, 2008-01-22 at 14:58 -0800, Greg KH wrote:
On Fri, Jan 18, 2008 at 09:56:28AM +0800, Shaohua Li wrote:
v3-v2, fixed the issues Matthew Wilcox raised.
PCI
On Tue, 2008-01-22 at 14:58 -0800, Greg KH wrote:
> On Fri, Jan 18, 2008 at 09:56:28AM +0800, Shaohua Li wrote:
> > v3->v2, fixed the issues Matthew Wilcox raised.
> >
> > PCI Express ASPM defines a protocol for PCI Express components in the D0
> > state to reduce Link power by placing their
On Fri, Jan 18, 2008 at 09:56:28AM +0800, Shaohua Li wrote:
> v3->v2, fixed the issues Matthew Wilcox raised.
>
> PCI Express ASPM defines a protocol for PCI Express components in the D0
> state to reduce Link power by placing their Links into a low power state
> and instructing the other end of
On Fri, Jan 18, 2008 at 09:56:28AM +0800, Shaohua Li wrote:
v3-v2, fixed the issues Matthew Wilcox raised.
PCI Express ASPM defines a protocol for PCI Express components in the D0
state to reduce Link power by placing their Links into a low power state
and instructing the other end of the
On Tue, 2008-01-22 at 14:58 -0800, Greg KH wrote:
On Fri, Jan 18, 2008 at 09:56:28AM +0800, Shaohua Li wrote:
v3-v2, fixed the issues Matthew Wilcox raised.
PCI Express ASPM defines a protocol for PCI Express components in the D0
state to reduce Link power by placing their Links into a
v3->v2, fixed the issues Matthew Wilcox raised.
PCI Express ASPM defines a protocol for PCI Express components in the D0
state to reduce Link power by placing their Links into a low power state
and instructing the other end of the Link to do likewise. This
capability allows hardware-autonomous,
v3-v2, fixed the issues Matthew Wilcox raised.
PCI Express ASPM defines a protocol for PCI Express components in the D0
state to reduce Link power by placing their Links into a low power state
and instructing the other end of the Link to do likewise. This
capability allows hardware-autonomous,
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