On 3.2.2016 03:30, Josh Cartwright wrote:
> The Zynq has a bug where the L2 cache will return invalid data in some
> circumstances unless the L2C_RAM register is set to 0x20202 before the first
> enabling of the L2 cache.
>
> The Xilinx-recommended solution to this problem is to ensure that early
The Zynq has a bug where the L2 cache will return invalid data in some
circumstances unless the L2C_RAM register is set to 0x20202 before the first
enabling of the L2 cache.
The Xilinx-recommended solution to this problem is to ensure that early one of
the earlier bootstages correctly initialize L
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