Re: [PATCH 0/2] Add bcm2835aux interrupt controller

2017-06-08 Thread Florian Fainelli
On 06/08/2017 02:55 AM, Phil Elwell wrote: > On 07/06/2017 21:58, Florian Fainelli wrote: >> On 06/07/2017 04:11 AM, Phil Elwell wrote: >>> Devices in the AUX block share a common interrupt line, with a register >>> indicating which devices have active IRQs. Expose this as a nested >>> interrupt co

Re: [PATCH 0/2] Add bcm2835aux interrupt controller

2017-06-08 Thread Phil Elwell
On 07/06/2017 21:58, Florian Fainelli wrote: > On 06/07/2017 04:11 AM, Phil Elwell wrote: >> Devices in the AUX block share a common interrupt line, with a register >> indicating which devices have active IRQs. Expose this as a nested >> interrupt controller to avoid IRQ sharing problems (easily ob

Re: [PATCH 0/2] Add bcm2835aux interrupt controller

2017-06-07 Thread Florian Fainelli
On 06/07/2017 04:11 AM, Phil Elwell wrote: > Devices in the AUX block share a common interrupt line, with a register > indicating which devices have active IRQs. Expose this as a nested > interrupt controller to avoid IRQ sharing problems (easily observed if > UART1 and SPI1/2 are enabled simultane

Re: [PATCH 0/2] Add bcm2835aux interrupt controller

2017-06-07 Thread Phil Elwell
On 07/06/2017 21:37, Stefan Wahren wrote: Hi Phil, Phil Elwell hat am 7. Juni 2017 um 13:11 geschrieben: Devices in the AUX block share a common interrupt line, with a register indicating which devices have active IRQs. Expose this as a nested interrupt controller to avoid IRQ sharing proble

Re: [PATCH 0/2] Add bcm2835aux interrupt controller

2017-06-07 Thread Stefan Wahren
Hi Phil, > Phil Elwell hat am 7. Juni 2017 um 13:11 geschrieben: > > > Devices in the AUX block share a common interrupt line, with a register > indicating which devices have active IRQs. Expose this as a nested > interrupt controller to avoid IRQ sharing problems (easily observed if > UART1 an

[PATCH 0/2] Add bcm2835aux interrupt controller

2017-06-07 Thread Phil Elwell
Devices in the AUX block share a common interrupt line, with a register indicating which devices have active IRQs. Expose this as a nested interrupt controller to avoid IRQ sharing problems (easily observed if UART1 and SPI1/2 are enabled simultaneously). The interrupt functionality could arguably