Hi Mike,
Two updates for the arch-vt8500 clock code:
#1: Add support for the WM8850 PLL.
#2: Remove a second divisor check in vt8500_dclk_set_rate() which causes the
divisor to be round-down too low.
Regards
Tony Prisk
Tony Prisk (2):
clk: vt8500: Add support for clocks on the WM8850 SoCs
clk: vt8500: Remove unnecessary divisor adjustment in
vtwm_dclk_set_rate()
Documentation/devicetree/bindings/clock/vt8500.txt | 2 +
drivers/clk/clk-vt8500.c | 75 ++++++++++++++++++--
2 files changed, 73 insertions(+), 4 deletions(-)
--
1.7.9.5
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