On Wed, 04 Apr 2018 22:02:29 PDT (-0700), alan...@andestech.com wrote:
On Tue, Apr 03, 2018 at 03:45:17PM -0700, Palmer Dabbelt wrote:
On Tue, 03 Apr 2018 07:29:02 PDT (-0700), alan...@andestech.com wrote:
>On Mon, Apr 02, 2018 at 08:15:44PM -0700, Palmer Dabbelt wrote:
>>On Mon, 02 Apr 2018 05:
On Tue, Apr 03, 2018 at 03:45:17PM -0700, Palmer Dabbelt wrote:
> On Tue, 03 Apr 2018 07:29:02 PDT (-0700), alan...@andestech.com wrote:
> >On Mon, Apr 02, 2018 at 08:15:44PM -0700, Palmer Dabbelt wrote:
> >>On Mon, 02 Apr 2018 05:31:22 PDT (-0700), alan...@andestech.com wrote:
> >>>This implements
On Mon, 02 Apr 2018 05:31:22 PDT (-0700), alan...@andestech.com wrote:
This implements the baseline PMU for RISC-V platforms.
To ease future PMU portings, a guide is also written, containing
perf concepts, arch porting practices and some hints.
Changes in v2:
- Fix the bug reported by Alex, wh
This implements the baseline PMU for RISC-V platforms.
To ease future PMU portings, a guide is also written, containing
perf concepts, arch porting practices and some hints.
Changes in v2:
- Fix the bug reported by Alex, which was caused by not sufficient
initialization. Check https://lkml.o
This implements the baseline PMU for RISC-V platforms.
To ease the future PMU portings, a guide is also written, containing
perf concepts, arch porting practices and some hints.
Alan Kao (2):
perf: riscv: preliminary RISC-V support
perf: riscv: Add Document for Future Porting Guide
Document
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