On Thu, Jul 14, 2016 at 07:20:16PM -0700, Andrey Pronin wrote:
> This patchset adds a TCG TPM2.0 PTP FIFO compliant interface for
> Cr50 chip on SPI.
>
> Depends on the following patches by Andrey Pronin
> that add new members to phy_ops in tpm_tis_core:
> - tpm: support
On Thu, Jul 14, 2016 at 07:20:16PM -0700, Andrey Pronin wrote:
> This patchset adds a TCG TPM2.0 PTP FIFO compliant interface for
> Cr50 chip on SPI.
>
> Depends on the following patches by Andrey Pronin
> that add new members to phy_ops in tpm_tis_core:
> - tpm: support driver-specific sysfs
On Thu, Jul 14, 2016 at 09:28:14PM -0600, Jason Gunthorpe wrote:
> On Thu, Jul 14, 2016 at 07:50:26PM -0700, Andrey Pronin wrote:
> > Yes, it has a TCG-compliant interface, however, there are several things
> > specific to this device:
> > - need to ensure a certain delay between spi
On Thu, Jul 14, 2016 at 09:28:14PM -0600, Jason Gunthorpe wrote:
> On Thu, Jul 14, 2016 at 07:50:26PM -0700, Andrey Pronin wrote:
> > Yes, it has a TCG-compliant interface, however, there are several things
> > specific to this device:
> > - need to ensure a certain delay between spi
On Thu, Jul 14, 2016 at 07:50:26PM -0700, Andrey Pronin wrote:
> Yes, it has a TCG-compliant interface, however, there are several things
> specific to this device:
> - need to ensure a certain delay between spi transactions, or else
>the chip can miss several first bytes.
> - if there is no
On Thu, Jul 14, 2016 at 07:50:26PM -0700, Andrey Pronin wrote:
> Yes, it has a TCG-compliant interface, however, there are several things
> specific to this device:
> - need to ensure a certain delay between spi transactions, or else
>the chip can miss several first bytes.
> - if there is no
On Thu, Jul 14, 2016 at 07:28:55PM -0700, Peter Huewe wrote:
> Am 14. Juli 2016 19:20:16 GMT-07:00, schrieb Andrey Pronin
> :
> >This patchset adds a TCG TPM2.0 PTP FIFO compliant interface for
> >Cr50 chip on SPI.
> >
> >Depends on the following patches by Andrey Pronin
>
On Thu, Jul 14, 2016 at 07:28:55PM -0700, Peter Huewe wrote:
> Am 14. Juli 2016 19:20:16 GMT-07:00, schrieb Andrey Pronin
> :
> >This patchset adds a TCG TPM2.0 PTP FIFO compliant interface for
> >Cr50 chip on SPI.
> >
> >Depends on the following patches by Andrey Pronin
> >
> >that add new
Am 14. Juli 2016 19:20:16 GMT-07:00, schrieb Andrey Pronin
:
>This patchset adds a TCG TPM2.0 PTP FIFO compliant interface for
>Cr50 chip on SPI.
>
>Depends on the following patches by Andrey Pronin
>
>that add new members to phy_ops in tpm_tis_core:
Am 14. Juli 2016 19:20:16 GMT-07:00, schrieb Andrey Pronin
:
>This patchset adds a TCG TPM2.0 PTP FIFO compliant interface for
>Cr50 chip on SPI.
>
>Depends on the following patches by Andrey Pronin
>
>that add new members to phy_ops in tpm_tis_core:
> - tpm: support driver-specific sysfs attrs
This patchset adds a TCG TPM2.0 PTP FIFO compliant interface for
Cr50 chip on SPI.
Depends on the following patches by Andrey Pronin
that add new members to phy_ops in tpm_tis_core:
- tpm: support driver-specific sysfs attrs in tpm_tis_core
- tpm_tis_core: add optional
This patchset adds a TCG TPM2.0 PTP FIFO compliant interface for
Cr50 chip on SPI.
Depends on the following patches by Andrey Pronin
that add new members to phy_ops in tpm_tis_core:
- tpm: support driver-specific sysfs attrs in tpm_tis_core
- tpm_tis_core: add optional max xfer size check
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