On Tue, Nov 17, 2020 at 11:04:57PM +0530, Vidya Sagar wrote:
[...]
> > IIUC we should:
> >
> > (1) apply
> > https://patchwork.kernel.org/project/linux-pci/patch/20201026181652.418729-1-r...@kernel.org
> > (2) apply [1,2] from this series
> >
> > For (2), are they rebased against v5.10-rc3
Hi Lorenzo & Bjorn,
Sorry to bother you.
Could you please take a look at the patches-1 & 2 from this series?
Thanks,
Vidya Sagar
On 11/4/2020 1:16 PM, Vidya Sagar wrote:
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Lorenzo / Bjorn,
Could you please review patches-1 & 2 in this
On 26/10/2020 12:32, Thierry Reding wrote:
> On Sat, Oct 24, 2020 at 04:03:41AM +, Jingoo Han wrote:
>> On 10/23/20, 3:57 PM, Vidya Sagar wrote:
>>>
>>> This patch series adds support for configuring the DesignWare IP's ATU
>>> region for prefetchable memory translations.
>>> It first starts
Lorenzo / Bjorn,
Could you please review patches-1 & 2 in this series?
For the third patch, we already went with Rob's patch @
http://patchwork.ozlabs.org/project/linux-pci/patch/20201026154852.221483-1-r...@kernel.org/
Thanks,
Vidya Sagar
On 10/26/2020 6:02 PM, Thierry Reding wrote:
On Sat,
On Sat, Oct 24, 2020 at 04:03:41AM +, Jingoo Han wrote:
> On 10/23/20, 3:57 PM, Vidya Sagar wrote:
> >
> > This patch series adds support for configuring the DesignWare IP's ATU
> > region for prefetchable memory translations.
> > It first starts by flagging a warning if the size of
On 10/23/20, 3:57 PM, Vidya Sagar wrote:
>
> This patch series adds support for configuring the DesignWare IP's ATU
> region for prefetchable memory translations.
> It first starts by flagging a warning if the size of non-prefetchable
> aperture goes beyond 32-bit as PCIe spec doesn't allow it.
>
This patch series adds support for configuring the DesignWare IP's ATU
region for prefetchable memory translations.
It first starts by flagging a warning if the size of non-prefetchable
aperture goes beyond 32-bit as PCIe spec doesn't allow it.
And then adds required support for programming the
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