Re: [PATCH 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

2017-04-27 Thread Sunil Kovvuri
On Thu, Apr 27, 2017 at 7:09 PM, Robert Richter wrote: > On 27.04.17 17:16:21, Geetha sowjanya wrote: >> From: Geetha >> >> Cavium CN99xx SMMUv3 implementation has two Silicon Erratas. >> 1. Errata ID #74 >>SMMU register alias Page 1 is not implemented >> 2. Errata ID #126 >>SMMU doesnt s

Re: [PATCH 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

2017-04-27 Thread Robert Richter
On 27.04.17 17:16:21, Geetha sowjanya wrote: > From: Geetha > > Cavium CN99xx SMMUv3 implementation has two Silicon Erratas. > 1. Errata ID #74 >SMMU register alias Page 1 is not implemented > 2. Errata ID #126 >SMMU doesnt support unique IRQ lines for gerror, eventq and cmdq-sync > > Th

[PATCH 0/3] Cavium ThunderX2 SMMUv3 errata workarounds

2017-04-27 Thread Geetha sowjanya
From: Geetha Cavium CN99xx SMMUv3 implementation has two Silicon Erratas. 1. Errata ID #74 SMMU register alias Page 1 is not implemented 2. Errata ID #126 SMMU doesnt support unique IRQ lines for gerror, eventq and cmdq-sync The following patchset does software workaround for these two err