Re: [PATCH 0/5] x86, MSI, AHCI: Support multiple MSIs

2012-08-17 Thread Alexander Gordeev
On Thu, Aug 16, 2012 at 12:19:43PM -0400, Jeff Garzik wrote: > 1) AHCI takes a host-wide lock during interrupt processing, which > quite reduces the value of "interrupts generated by different > ports could be serviced on different CPUs" > > 2) We do not put AHCI-specific code in libata-core. Try

Re: [PATCH 0/5] x86, MSI, AHCI: Support multiple MSIs

2012-08-16 Thread Jeff Garzik
On 08/16/2012 10:45 AM, Alexander Gordeev wrote: Currently multiple MSI mode is limited to a single vector per device (at least on x86 and PPC). This series breathes life into pci_enable_msi_block() and makes it possible to set interrupt affinity for multiple IRQs, similarly to MSI-X. Yet, only f

[PATCH 0/5] x86, MSI, AHCI: Support multiple MSIs

2012-08-16 Thread Alexander Gordeev
Currently multiple MSI mode is limited to a single vector per device (at least on x86 and PPC). This series breathes life into pci_enable_msi_block() and makes it possible to set interrupt affinity for multiple IRQs, similarly to MSI-X. Yet, only for x86 and only when IOMMUs are present. Although