[PATCH 0/8] phy: rockchip-usb: correct pll handling and usb-uart

Patches 1-7 fix a long-standing issue with the clock-tree of Rockchip SoCs namely our ignorance of the usbphy-internal pll that creates the needed 480MHz but is also a supply-clock back to the core clock-controller in Rockchip SoCs. Till now that was worked around using a virtual clock in the cru

[PATCH 0/8] phy: rockchip-usb: correct pll handling and usb-uart

Patches 1-7 fix a long-standing issue with the clock-tree of Rockchip SoCs namely our ignorance of the usbphy-internal pll that creates the needed 480MHz but is also a supply-clock back to the core clock-controller in Rockchip SoCs. Till now that was worked around using a virtual clock in the cru