Re: [PATCH 0/8] pinctrl: aspeed: Fixes for core and g5, implement remaining pins

2016-10-10 Thread Andrew Jeffery
On Mon, 2016-10-10 at 09:59 +0200, Linus Walleij wrote: > On Tue, Sep 27, 2016 at 4:50 PM, Andrew Jeffery wrote: > > > > > The initial Aspeed pinctrl patches implemented a subset of pins for each of > > the > > g4 and g5 SoCs. This series provides a number of fixes to the initial > > patches,

Re: [PATCH 0/8] pinctrl: aspeed: Fixes for core and g5, implement remaining pins

2016-10-10 Thread Linus Walleij
On Tue, Sep 27, 2016 at 4:50 PM, Andrew Jeffery wrote: > The initial Aspeed pinctrl patches implemented a subset of pins for each of > the > g4 and g5 SoCs. This series provides a number of fixes to the initial patches, > mostly for issues identified in the g5 driver. The fixes account for the f

[PATCH 0/8] pinctrl: aspeed: Fixes for core and g5, implement remaining pins

2016-09-27 Thread Andrew Jeffery
Hi all, The initial Aspeed pinctrl patches implemented a subset of pins for each of the g4 and g5 SoCs. This series provides a number of fixes to the initial patches, mostly for issues identified in the g5 driver. The fixes account for the first half of the series (up to and including "pinctrl: as