On Fri, Oct 30, 2015 at 03:52:17PM +0100, Daniel Vetter wrote:
> On Fri, Oct 30, 2015 at 03:20:46PM +0100, Maxime Ripard wrote:
> > Hi everyone,
> >
> > The Allwinner SoCs (except for the very latest ones) all share the
> > same set of controllers, loosely coupled together to form the display
> >
Hi Maxime,
On Fri, Oct 30, 2015 at 10:20 PM, Maxime Ripard
wrote:
> Maxime Ripard (19):
> clk: sunxi: Add display clock
> clk: sunxi: Add PLL3 clock
> clk: sunxi: Add TCON channel0 clock
> clk: sunxi: Add TCON channel1 clock
> clk: sunxi: add DRAM gates
> clk: sunxi: Add Allwinner R8
On Fri, Oct 30, 2015 at 03:20:46PM +0100, Maxime Ripard wrote:
> Hi everyone,
>
> The Allwinner SoCs (except for the very latest ones) all share the
> same set of controllers, loosely coupled together to form the display
> pipeline.
>
> Depending on the SoC, the number of instances of the control
Hi everyone,
The Allwinner SoCs (except for the very latest ones) all share the
same set of controllers, loosely coupled together to form the display
pipeline.
Depending on the SoC, the number of instances of the controller will
change (2 instances of each in the A10, only one in the A13, for
exa
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