Re: [PATCH 02/14] cxl/mem: Map memory device registers

2021-02-03 Thread Christoph Hellwig
On Tue, Feb 02, 2021 at 10:31:51AM -0800, Ben Widawsky wrote: > > > + if (reg_type == CXL_REGLOC_RBI_MEMDEV) { > > > + rc = 0; > > > + cxlm = cxl_mem_create(pdev, reg_lo, reg_hi); > > > + if (!cxlm) > > > + rc =

Re: [PATCH 02/14] cxl/mem: Map memory device registers

2021-02-02 Thread Ben Widawsky
On 21-02-02 18:04:41, Christoph Hellwig wrote: > Any reason not to merge a bunch of patches? Both this one and > the previous one are rather useless on their own, making review > harder than necessary. > As this is an initial driver, there's obviously no functional/regression testing value in

Re: [PATCH 02/14] cxl/mem: Map memory device registers

2021-02-02 Thread Christoph Hellwig
Any reason not to merge a bunch of patches? Both this one and the previous one are rather useless on their own, making review harder than necessary. > + * cxl_mem_create() - Create a new cxl_mem. > + * @pdev: The pci device associated with the new cxl_mem. > + * @reg_lo: Lower 32b of the

Re: [PATCH 02/14] cxl/mem: Map memory device registers

2021-02-01 Thread Jonathan Cameron
On Mon, 1 Feb 2021 08:46:24 -0800 Ben Widawsky wrote: > On 21-01-30 15:51:42, David Rientjes wrote: > > On Fri, 29 Jan 2021, Ben Widawsky wrote: > > > > > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > > > new file mode 100644 > > > index ..d81d0ba4617c > > > --- /dev/null >

Re: [PATCH 02/14] cxl/mem: Map memory device registers

2021-02-01 Thread Konrad Rzeszutek Wilk
> > - return 0; > + rc = -ENXIO; > + for (i = regloc; i < regloc + 0x24; i += 8) { This 0x24, 8, and > + u32 reg_lo, reg_hi; > + u8 reg_type; > + > + /* "register low and high" contain other bits */ > + pci_read_config_dword(pdev, i,

Re: [PATCH 02/14] cxl/mem: Map memory device registers

2021-02-01 Thread Ben Widawsky
On 21-01-30 15:51:42, David Rientjes wrote: > On Fri, 29 Jan 2021, Ben Widawsky wrote: > > > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > > new file mode 100644 > > index ..d81d0ba4617c > > --- /dev/null > > +++ b/drivers/cxl/cxl.h > > @@ -0,0 +1,17 @@ > > +/*

Re: [PATCH 02/14] cxl/mem: Map memory device registers

2021-01-30 Thread David Rientjes
On Fri, 29 Jan 2021, Ben Widawsky wrote: > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > new file mode 100644 > index ..d81d0ba4617c > --- /dev/null > +++ b/drivers/cxl/cxl.h > @@ -0,0 +1,17 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* Copyright(c) 2020 Intel

[PATCH 02/14] cxl/mem: Map memory device registers

2021-01-29 Thread Ben Widawsky
All the necessary bits are initialized in order to find and map the register space for CXL Memory Devices. This is accomplished by using the Register Locator DVSEC (CXL 2.0 - 8.1.9.1) to determine which PCI BAR to use, and how much of an offset from that BAR should be added. If the memory device