Re: [PATCH 02/17] fpga: dfl: fme: align PR buffer size per PR datawidth

2019-03-28 Thread Alan Tull
On Mon, Mar 25, 2019 at 7:44 PM Wu Hao wrote: > > On Mon, Mar 25, 2019 at 12:50:40PM -0500, Alan Tull wrote: > > On Sun, Mar 24, 2019 at 10:23 PM Wu Hao wrote: > > > > Hi Hao, > > > > Looks good, one question below. > > > > > > > > Current driver checks if input bitstream file size is aligned or

Re: [PATCH 02/17] fpga: dfl: fme: align PR buffer size per PR datawidth

2019-03-25 Thread Wu Hao
On Mon, Mar 25, 2019 at 12:50:40PM -0500, Alan Tull wrote: > On Sun, Mar 24, 2019 at 10:23 PM Wu Hao wrote: > > Hi Hao, > > Looks good, one question below. > > > > > Current driver checks if input bitstream file size is aligned or > > not per PR data width (default 32bits). It requires one addi

Re: [PATCH 02/17] fpga: dfl: fme: align PR buffer size per PR datawidth

2019-03-25 Thread Alan Tull
On Sun, Mar 24, 2019 at 10:23 PM Wu Hao wrote: Hi Hao, Looks good, one question below. > > Current driver checks if input bitstream file size is aligned or > not per PR data width (default 32bits). It requires one additional > step for end user when they generate the bitstream file, padding > e

[PATCH 02/17] fpga: dfl: fme: align PR buffer size per PR datawidth

2019-03-24 Thread Wu Hao
Current driver checks if input bitstream file size is aligned or not per PR data width (default 32bits). It requires one additional step for end user when they generate the bitstream file, padding extra zeros to bitstream file to align its size per PR data width, but they don't have to as hardware