On Thu, May 04, 2017 at 10:13:41AM -0500, Li, Yi wrote:
> hi Hao
>
>
> On 3/30/2017 7:08 AM, Wu Hao wrote:
> >From: Xiao Guangrong
> >
> >Device Featuer List structure creates a link list of feature headers
> >within the MMIO space to provide an extensiable way of adding features.
> >
> >The Int
hi Hao
On 3/30/2017 7:08 AM, Wu Hao wrote:
From: Xiao Guangrong
Device Featuer List structure creates a link list of feature headers
within the MMIO space to provide an extensiable way of adding features.
The Intel FPGA PCIe driver walks through the feature headers to enumerate
feature devic
> On Wed, Apr 5, 2017 at 6:58 AM, Wu Hao wrote:
> > On Mon, Apr 03, 2017 at 04:44:15PM -0500, Alan Tull wrote:
> >> On Thu, Mar 30, 2017 at 7:08 AM, Wu Hao wrote:
> >> > From: Xiao Guangrong
> >> >
> >> > Device Featuer List structure creates a link list of feature headers
> >> > within the MMIO
On Wed, Apr 5, 2017 at 6:58 AM, Wu Hao wrote:
> On Mon, Apr 03, 2017 at 04:44:15PM -0500, Alan Tull wrote:
>> On Thu, Mar 30, 2017 at 7:08 AM, Wu Hao wrote:
>> > From: Xiao Guangrong
>> >
>> > Device Featuer List structure creates a link list of feature headers
>> > within the MMIO space to prov
On Tue, Apr 04, 2017 at 05:09:23PM -0500, Alan Tull wrote:
> On Thu, Mar 30, 2017 at 7:08 AM, Wu Hao wrote:
> > From: Xiao Guangrong
> >
> > Device Featuer List structure creates a link list of feature headers
> > within the MMIO space to provide an extensiable way of adding features.
> >
> > The
On Mon, Apr 03, 2017 at 07:44:55PM -0700, Moritz Fischer wrote:
> Xiao,
>
> few nits inline, I'll need to come back to this once I went over the
> rest of the patchset ;-)
Sure, Thanks for your comments and review. :)
>
> On Thu, Mar 30, 2017 at 08:08:04PM +0800, Wu Hao wrote:
> > From: Xiao Gu
On Mon, Apr 03, 2017 at 04:44:15PM -0500, Alan Tull wrote:
> On Thu, Mar 30, 2017 at 7:08 AM, Wu Hao wrote:
> > From: Xiao Guangrong
> >
> > Device Featuer List structure creates a link list of feature headers
> > within the MMIO space to provide an extensiable way of adding features.
> >
> > The
On Thu, Mar 30, 2017 at 7:08 AM, Wu Hao wrote:
> From: Xiao Guangrong
>
> Device Featuer List structure creates a link list of feature headers
> within the MMIO space to provide an extensiable way of adding features.
>
> The Intel FPGA PCIe driver walks through the feature headers to enumerate
>
Xiao,
few nits inline, I'll need to come back to this once I went over the
rest of the patchset ;-)
On Thu, Mar 30, 2017 at 08:08:04PM +0800, Wu Hao wrote:
> From: Xiao Guangrong
>
> Device Featuer List structure creates a link list of feature headers
> within the MMIO space to provide an exten
On Thu, Mar 30, 2017 at 7:08 AM, Wu Hao wrote:
> From: Xiao Guangrong
>
> Device Featuer List structure creates a link list of feature headers
> within the MMIO space to provide an extensiable way of adding features.
>
> The Intel FPGA PCIe driver walks through the feature headers to enumerate
>
From: Xiao Guangrong
Device Featuer List structure creates a link list of feature headers
within the MMIO space to provide an extensiable way of adding features.
The Intel FPGA PCIe driver walks through the feature headers to enumerate
feature devices, FPGA Management Engine (FME) and FPGA Port
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