Re: [PATCH 04/32] x86/intel_rdt: Add L3 cache capacity bitmask management

On Sat, 23 Jul 2016, Marcelo Tosatti wrote: On Fri, Jul 22, 2016 at 02:43:23PM -0700, Luck, Tony wrote: On Fri, Jul 22, 2016 at 04:12:04AM -0300, Marcelo Tosatti wrote: How does this patchset handle the following condition: 6) Create reservations in such a way that the sum is larger than

Re: [PATCH 04/32] x86/intel_rdt: Add L3 cache capacity bitmask management

On Sat, 23 Jul 2016, Marcelo Tosatti wrote: On Fri, Jul 22, 2016 at 02:43:23PM -0700, Luck, Tony wrote: On Fri, Jul 22, 2016 at 04:12:04AM -0300, Marcelo Tosatti wrote: How does this patchset handle the following condition: 6) Create reservations in such a way that the sum is larger than

Re: [PATCH 04/32] x86/intel_rdt: Add L3 cache capacity bitmask management

You must specify a mask for each L3 cache. So you can achieve your 80/80 split either with one rdtgroup that has an 80% mask on each of the sockets and using affinity to make one VM run only on CPUs on one socket and the second VM on the other. Or separate rdtgroups for each VM that give them

Re: [PATCH 04/32] x86/intel_rdt: Add L3 cache capacity bitmask management

You must specify a mask for each L3 cache. So you can achieve your 80/80 split either with one rdtgroup that has an 80% mask on each of the sockets and using affinity to make one VM run only on CPUs on one socket and the second VM on the other. Or separate rdtgroups for each VM that give them

Re: [PATCH 04/32] x86/intel_rdt: Add L3 cache capacity bitmask management

On Fri, Jul 22, 2016 at 02:43:23PM -0700, Luck, Tony wrote: > On Fri, Jul 22, 2016 at 04:12:04AM -0300, Marcelo Tosatti wrote: > > How does this patchset handle the following condition: > > > > 6) Create reservations in such a way that the sum is larger than > > total amount of cache, and CPU

Re: [PATCH 04/32] x86/intel_rdt: Add L3 cache capacity bitmask management

On Fri, Jul 22, 2016 at 02:43:23PM -0700, Luck, Tony wrote: > On Fri, Jul 22, 2016 at 04:12:04AM -0300, Marcelo Tosatti wrote: > > How does this patchset handle the following condition: > > > > 6) Create reservations in such a way that the sum is larger than > > total amount of cache, and CPU

Re: [PATCH 04/32] x86/intel_rdt: Add L3 cache capacity bitmask management

On Fri, Jul 22, 2016 at 04:12:04AM -0300, Marcelo Tosatti wrote: > How does this patchset handle the following condition: > > 6) Create reservations in such a way that the sum is larger than > total amount of cache, and CPU pinning (example from Karen Noel): > > VM-1 on socket-1 with 80% of

Re: [PATCH 04/32] x86/intel_rdt: Add L3 cache capacity bitmask management

On Fri, Jul 22, 2016 at 04:12:04AM -0300, Marcelo Tosatti wrote: > How does this patchset handle the following condition: > > 6) Create reservations in such a way that the sum is larger than > total amount of cache, and CPU pinning (example from Karen Noel): > > VM-1 on socket-1 with 80% of

Re: [PATCH 04/32] x86/intel_rdt: Add L3 cache capacity bitmask management

On Tue, Jul 12, 2016 at 06:02:37PM -0700, Fenghua Yu wrote: > From: Vikas Shivappa > > This patch adds different APIs to manage the L3 cache capacity bitmask. > The capacity bit mask(CBM) needs to have only contiguous bits set. The > current implementation has a

Re: [PATCH 04/32] x86/intel_rdt: Add L3 cache capacity bitmask management

On Tue, Jul 12, 2016 at 06:02:37PM -0700, Fenghua Yu wrote: > From: Vikas Shivappa > > This patch adds different APIs to manage the L3 cache capacity bitmask. > The capacity bit mask(CBM) needs to have only contiguous bits set. The > current implementation has a global CBM for each class of

[PATCH 04/32] x86/intel_rdt: Add L3 cache capacity bitmask management

From: Vikas Shivappa This patch adds different APIs to manage the L3 cache capacity bitmask. The capacity bit mask(CBM) needs to have only contiguous bits set. The current implementation has a global CBM for each class of service id. There are APIs added to update

[PATCH 04/32] x86/intel_rdt: Add L3 cache capacity bitmask management

From: Vikas Shivappa This patch adds different APIs to manage the L3 cache capacity bitmask. The capacity bit mask(CBM) needs to have only contiguous bits set. The current implementation has a global CBM for each class of service id. There are APIs added to update the CBM via MSR write to