On Tue, Oct 27, 2020 at 10:31:19AM +0100, Paul Kocialkowski wrote:
> Hi,
>
> On Mon 26 Oct 20, 17:00, Maxime Ripard wrote:
> > On Fri, Oct 23, 2020 at 07:45:37PM +0200, Paul Kocialkowski wrote:
> > > Bits related to the interface data width do not have any effect when
> > > the CSI controller is t
Hi,
On Mon 26 Oct 20, 17:00, Maxime Ripard wrote:
> On Fri, Oct 23, 2020 at 07:45:37PM +0200, Paul Kocialkowski wrote:
> > Bits related to the interface data width do not have any effect when
> > the CSI controller is taking input from the MIPI CSI-2 controller.
>
> I guess it would be clearer to
On Fri, Oct 23, 2020 at 07:45:37PM +0200, Paul Kocialkowski wrote:
> Bits related to the interface data width do not have any effect when
> the CSI controller is taking input from the MIPI CSI-2 controller.
I guess it would be clearer to mention that the data width is only
applicable for parallel
Bits related to the interface data width do not have any effect when
the CSI controller is taking input from the MIPI CSI-2 controller.
In prevision of adding support for this case, set these bits
conditionally so there is no ambiguity.
Co-developed-by: Kévin L'hôpital
Signed-off-by: Kévin L'hôp
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