Re: [PATCH 06/10] mmc: dw_mmc-pltfm: add Rockchip variant

2013-06-06 Thread Andy Shevchenko
On Mon, Jun 3, 2013 at 1:59 AM, Heiko Stübner wrote: > Cortex-A9 SoCs from Rockchip use a slightly modified variant of dw_mmc > controllers that seems to require the SDMMC_CMD_USE_HOLD_REG bit to > always be set. > > There also seem to be no other modifications (additional register etc) > present,

Re: [PATCH 06/10] mmc: dw_mmc-pltfm: add Rockchip variant

2013-06-05 Thread Heiko Stübner
Am Mittwoch, 5. Juni 2013, 16:00:43 schrieb Seungwon Jeon: > On 06/03/13 7:59 AM, Heiko Stübner wrote: > > Cortex-A9 SoCs from Rockchip use a slightly modified variant of dw_mmc > > controllers that seems to require the SDMMC_CMD_USE_HOLD_REG bit to > > always be set. > > > > There also seem to be

RE: [PATCH 06/10] mmc: dw_mmc-pltfm: add Rockchip variant

2013-06-05 Thread Seungwon Jeon
On 06/03/13 7:59 AM, Heiko Stübner wrote: > Cortex-A9 SoCs from Rockchip use a slightly modified variant of dw_mmc > controllers that seems to require the SDMMC_CMD_USE_HOLD_REG bit to > always be set. > > There also seem to be no other modifications (additional register etc) > present, so to keep

Re: [PATCH 06/10] mmc: dw_mmc-pltfm: add Rockchip variant

2013-06-04 Thread Heiko Stübner
Am Dienstag, 4. Juni 2013, 06:06:39 schrieb Jaehoon Chung: > On 06/03/2013 07:59 AM, Heiko Stübner wrote: > > Cortex-A9 SoCs from Rockchip use a slightly modified variant of dw_mmc > > controllers that seems to require the SDMMC_CMD_USE_HOLD_REG bit to > > always be set. > > > > There also seem to

Re: [PATCH 06/10] mmc: dw_mmc-pltfm: add Rockchip variant

2013-06-03 Thread Jaehoon Chung
On 06/03/2013 07:59 AM, Heiko Stübner wrote: > Cortex-A9 SoCs from Rockchip use a slightly modified variant of dw_mmc > controllers that seems to require the SDMMC_CMD_USE_HOLD_REG bit to > always be set. > > There also seem to be no other modifications (additional register etc) > present, so to k

[PATCH 06/10] mmc: dw_mmc-pltfm: add Rockchip variant

2013-06-02 Thread Heiko Stübner
Cortex-A9 SoCs from Rockchip use a slightly modified variant of dw_mmc controllers that seems to require the SDMMC_CMD_USE_HOLD_REG bit to always be set. There also seem to be no other modifications (additional register etc) present, so to keep the footprint low, add this small variant to the pltf