This adds a SPI controller to the Microchip Sparx5 SoC

Reviewed-by: Alexandre Belloni <alexandre.bell...@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povl...@microchip.com>
---
 arch/arm64/boot/dts/microchip/sparx5.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi 
b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index b5f2d088af30e..daa216978887d 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -14,6 +14,7 @@ / {
        #size-cells = <1>;

        aliases {
+               spi0 = &spi0;
                serial0 = &uart0;
                serial1 = &uart1;
        };
@@ -144,6 +145,21 @@ uart1: serial@600102000 {
                        status = "disabled";
                };

+               spi0: spi@600104000 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       compatible = "microchip,sparx5-spi";
+                       reg = <0x6 0x00104000 0x40>, <0 0 0>,
+                             <0x3 0x0 0x4000000>;
+                       num-cs = <16>;
+                       reg-io-width = <4>;
+                       reg-shift = <2>;
+                       clocks = <&ahb_clk>;
+                       interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+
+                       status = "disabled";
+               };
+
                timer1: timer@600105000 {
                        compatible = "snps,dw-apb-timer";
                        reg = <0x6 0x00105000 0x1000>;
--
2.26.2

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