On Wed, 24 Jun 2015, Thomas Gleixner wrote:
On Tue, 23 Jun 2015, Vikas Shivappa wrote:
+/*
+ * cbm_update_msrs() - Updates all the existing IA32_L3_MASK_n MSRs
+ * which are one per CLOSid except IA32_L3_MASK_0 on the current package.
+ */
+static inline void cbm_update_msrs(void)
+{
+
On Tue, 23 Jun 2015, Vikas Shivappa wrote:
> +/*
> + * cbm_update_msrs() - Updates all the existing IA32_L3_MASK_n MSRs
> + * which are one per CLOSid except IA32_L3_MASK_0 on the current package.
> + */
> +static inline void cbm_update_msrs(void)
> +{
> + int maxid = boot_cpu_data.x86_cache_ma
This patch adds hot cpu support for Intel Cache allocation. Support
includes updating the cache bitmask MSRs IA32_L3_QOS_n when a new CPU
package comes online. The IA32_L3_QOS_n MSRs are one per Class of
service on each CPU package. The new package's MSRs are synchronized
with the values of existin
On Tue, 16 Jun 2015, Thomas Gleixner wrote:
On Tue, 16 Jun 2015, Vikas Shivappa wrote:
On Tue, 16 Jun 2015, Thomas Gleixner wrote:
On Fri, 12 Jun 2015, Vikas Shivappa wrote:
+static inline void intel_rdt_cpu_start(int cpu)
+{
+ struct intel_pqr_state *state = &per_cpu(pqr_state, cpu)
On Tue, 16 Jun 2015, Vikas Shivappa wrote:
> On Tue, 16 Jun 2015, Thomas Gleixner wrote:
>
> > On Fri, 12 Jun 2015, Vikas Shivappa wrote:
> > > +static inline void intel_rdt_cpu_start(int cpu)
> > > +{
> > > + struct intel_pqr_state *state = &per_cpu(pqr_state, cpu);
> > > +
> > > + state->closid
On Tue, 16 Jun 2015, Thomas Gleixner wrote:
On Fri, 12 Jun 2015, Vikas Shivappa wrote:
+static inline void intel_rdt_cpu_start(int cpu)
+{
+ struct intel_pqr_state *state = &per_cpu(pqr_state, cpu);
+
+ state->closid = 0;
+ mutex_lock(&rdt_group_mutex);
This is called from
On Fri, 12 Jun 2015, Vikas Shivappa wrote:
> +static inline void intel_rdt_cpu_start(int cpu)
> +{
> + struct intel_pqr_state *state = &per_cpu(pqr_state, cpu);
> +
> + state->closid = 0;
> + mutex_lock(&rdt_group_mutex);
This is called from CPU_STARTING, which runs on the starting cpu
This patch adds hot cpu support for Intel Cache allocation. Support
includes updating the cache bitmask MSRs IA32_L3_QOS_n when a new CPU
package comes online. The IA32_L3_QOS_n MSRs are one per Class of
service on each CPU package. The new package's MSRs are synchronized
with the values of existin
This patch adds hot cpu support for Intel Cache allocation. Support
includes updating the cache bitmask MSRs IA32_L3_QOS_n when a new CPU
package comes online. The IA32_L3_QOS_n MSRs are one per Class of
service on each CPU package. The new package's MSRs are synchronized
with the values of existin
This patch adds hot cpu support for Intel Cache allocation. Support
includes updating the cache bitmask MSRs IA32_L3_QOS_n when a new CPU
package comes online. The IA32_L3_QOS_n MSRs are one per Class of
service on each CPU package. The new package's MSRs are synchronized
with the values of existin
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