Re: [PATCH 09/22] clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output

2014-05-25 Thread Chen-Yu Tsai
Hi, On Mon, May 26, 2014 at 2:56 AM, Maxime Ripard wrote: > On Fri, May 23, 2014 at 03:51:12PM +0800, Chen-Yu Tsai wrote: >> Some clock modules on the A31 use PLL6x2 as one of their inputs. >> This patch changes the PLL6 implementation for A31 to a divs clock, >> i.e. clock with multiple outputs

Re: [PATCH 09/22] clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output

2014-05-25 Thread Maxime Ripard
On Fri, May 23, 2014 at 03:51:12PM +0800, Chen-Yu Tsai wrote: > Some clock modules on the A31 use PLL6x2 as one of their inputs. > This patch changes the PLL6 implementation for A31 to a divs clock, > i.e. clock with multiple outputs that have different dividers. > > This behavior is consistent wi

[PATCH 09/22] clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output

2014-05-23 Thread Chen-Yu Tsai
Some clock modules on the A31 use PLL6x2 as one of their inputs. This patch changes the PLL6 implementation for A31 to a divs clock, i.e. clock with multiple outputs that have different dividers. This behavior is consistent with previous SoC's by Allwinner. Signed-off-by: Chen-Yu Tsai --- drive