Hi,
On Mon, May 26, 2014 at 2:56 AM, Maxime Ripard
wrote:
> On Fri, May 23, 2014 at 03:51:12PM +0800, Chen-Yu Tsai wrote:
>> Some clock modules on the A31 use PLL6x2 as one of their inputs.
>> This patch changes the PLL6 implementation for A31 to a divs clock,
>> i.e. clock with multiple outputs
On Fri, May 23, 2014 at 03:51:12PM +0800, Chen-Yu Tsai wrote:
> Some clock modules on the A31 use PLL6x2 as one of their inputs.
> This patch changes the PLL6 implementation for A31 to a divs clock,
> i.e. clock with multiple outputs that have different dividers.
>
> This behavior is consistent wi
Some clock modules on the A31 use PLL6x2 as one of their inputs.
This patch changes the PLL6 implementation for A31 to a divs clock,
i.e. clock with multiple outputs that have different dividers.
This behavior is consistent with previous SoC's by Allwinner.
Signed-off-by: Chen-Yu Tsai
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