Re: [PATCH 1/1] AArch64: TCR_TG1_64K incorrectly sets TCR_EL1 bits [31:30]

2014-04-03 Thread Catalin Marinas
On Wed, Apr 02, 2014 at 06:21:29PM +0100, Joe Sylve wrote: > That makes sense and I agree, it's better to fix it now so that it > will be easier to add 16K paging later (on a side note is there any > reason not to add it now if someone was willing to do the work?). See another thread with the Sams

Re: [PATCH 1/1] AArch64: TCR_TG1_64K incorrectly sets TCR_EL1 bits [31:30]

2014-04-02 Thread Joe Sylve
Noted, thanks. On Wed, Apr 2, 2014 at 5:16 PM, Joe Perches wrote: > On Wed, 2014-04-02 at 17:10 -0500, Joe Sylve wrote: >> Should it? The reference manual refers to the architecture as AArch64. >> >> On Wed, Apr 2, 2014 at 4:44 PM, Joe Perches wrote: >> > On Wed, 2014-04-02 at 18:07 +0100, Cata

Re: [PATCH 1/1] AArch64: TCR_TG1_64K incorrectly sets TCR_EL1 bits [31:30]

2014-04-02 Thread Joe Perches
On Wed, 2014-04-02 at 17:10 -0500, Joe Sylve wrote: > Should it? The reference manual refers to the architecture as AArch64. > > On Wed, Apr 2, 2014 at 4:44 PM, Joe Perches wrote: > > On Wed, 2014-04-02 at 18:07 +0100, Catalin Marinas wrote: > >> On Wed, Apr 02, 2014 at 01:38:44PM +0100, Catalin

Re: [PATCH 1/1] AArch64: TCR_TG1_64K incorrectly sets TCR_EL1 bits [31:30]

2014-04-02 Thread Joe Sylve
Should it? The reference manual refers to the architecture as AArch64. On Wed, Apr 2, 2014 at 4:44 PM, Joe Perches wrote: > On Wed, 2014-04-02 at 18:07 +0100, Catalin Marinas wrote: >> On Wed, Apr 02, 2014 at 01:38:44PM +0100, Catalin Marinas wrote: >> > On Wed, Apr 02, 2014 at 05:00:38AM +0100,

Re: [PATCH 1/1] AArch64: TCR_TG1_64K incorrectly sets TCR_EL1 bits [31:30]

2014-04-02 Thread Joe Perches
On Wed, 2014-04-02 at 18:07 +0100, Catalin Marinas wrote: > On Wed, Apr 02, 2014 at 01:38:44PM +0100, Catalin Marinas wrote: > > On Wed, Apr 02, 2014 at 05:00:38AM +0100, Joe Sylve wrote: > > > Section D7.2.83 TCR_EL1, Translation Control Register (EL1) of the > > > latest ARM Architecture Referenc

Re: [PATCH 1/1] AArch64: TCR_TG1_64K incorrectly sets TCR_EL1 bits [31:30]

2014-04-02 Thread Joe Sylve
That makes sense and I agree, it's better to fix it now so that it will be easier to add 16K paging later (on a side note is there any reason not to add it now if someone was willing to do the work?). Your patch is exactly the solution that I had in my head to fix it if the spec was correct. There

Re: [PATCH 1/1] AArch64: TCR_TG1_64K incorrectly sets TCR_EL1 bits [31:30]

2014-04-02 Thread Catalin Marinas
On Wed, Apr 02, 2014 at 01:38:44PM +0100, Catalin Marinas wrote: > On Wed, Apr 02, 2014 at 05:00:38AM +0100, Joe Sylve wrote: > > Section D7.2.83 TCR_EL1, Translation Control Register (EL1) of the > > latest ARM Architecture Reference Manual, ARMv8, for ARMv8-A states > > that TCR_EL1 TG1 (bits [31

Re: [PATCH 1/1] AArch64: TCR_TG1_64K incorrectly sets TCR_EL1 bits [31:30]

2014-04-02 Thread Catalin Marinas
On Wed, Apr 02, 2014 at 05:00:38AM +0100, Joe Sylve wrote: > Section D7.2.83 TCR_EL1, Translation Control Register (EL1) of the > latest ARM Architecture Reference Manual, ARMv8, for ARMv8-A states > that TCR_EL1 TG1 (bits [31:30]) should be set to 11 for a 64KB > TTBR1_EL1 granule size. The mainli

[PATCH 1/1] AArch64: TCR_TG1_64K incorrectly sets TCR_EL1 bits [31:30]

2014-04-01 Thread Joe Sylve
Section D7.2.83 TCR_EL1, Translation Control Register (EL1) of the latest ARM Architecture Reference Manual, ARMv8, for ARMv8-A states that TCR_EL1 TG1 (bits [31:30]) should be set to 11 for a 64KB TTBR1_EL1 granule size. The mainline 3.14 kernel incorrectly sets those bits to 01 (which is a 16KB g