On Mon, 2020-09-21 at 12:25 +0300, Maxim Levitsky wrote:
> On Thu, 2020-09-17 at 09:11 -0700, Sean Christopherson wrote:
> > On Thu, Sep 17, 2020 at 02:07:23PM +0300, Maxim Levitsky wrote:
> > > MSR reads/writes should always access the L1 state, since the (nested)
> > > hypervisor should intercept
On Thu, 2020-09-17 at 09:14 -0700, Sean Christopherson wrote:
> On Thu, Sep 17, 2020 at 02:07:23PM +0300, Maxim Levitsky wrote:
> > +* Intel PRM states that MSR_IA32_TSC read adds the TSC offset
>
> One more nit, "Intel SDM" would be preferred as that's most commonly used in
> KVM chan
On Thu, 2020-09-17 at 09:11 -0700, Sean Christopherson wrote:
> On Thu, Sep 17, 2020 at 02:07:23PM +0300, Maxim Levitsky wrote:
> > MSR reads/writes should always access the L1 state, since the (nested)
> > hypervisor should intercept all the msrs it wants to adjust, and these
> > that it doesn't s
On Thu, Sep 17, 2020 at 02:07:23PM +0300, Maxim Levitsky wrote:
> MSR reads/writes should always access the L1 state, since the (nested)
> hypervisor should intercept all the msrs it wants to adjust, and these
> that it doesn't should be read by the guest as if the host had read it.
>
> However IA
On Thu, Sep 17, 2020 at 02:07:23PM +0300, Maxim Levitsky wrote:
> + * Intel PRM states that MSR_IA32_TSC read adds the TSC offset
One more nit, "Intel SDM" would be preferred as that's most commonly used in
KVM changelogs, and there are multiple PRM acronyms in Intel's dictionary
thes
MSR reads/writes should always access the L1 state, since the (nested)
hypervisor should intercept all the msrs it wants to adjust, and these
that it doesn't should be read by the guest as if the host had read it.
However IA32_TSC is an exception.Even when not intercepted, guest still
reads the va
6 matches
Mail list logo
